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Register Name:
0 x C800B058
Hex Offset Address:
Register
Universal Serial Bus Device Controller Interrupt Status Register 0
Description:
Access: Read/Write and Read-Only
31
Bits
31:8
7
6
5
4
3
2
1
0
8.5.21
UDC Status/Interrupt Register 1
8.5.21.1
Endpoint 8 Interrupt Request (IR8)
The interrupt request bit is set if the IM8 bit in the UDC Interrupt Control Register is
cleared and the IN packet complete (TPC) or Transmit Underrun (TUR) in UDC Endpoint
8 Control/Status Register is set.
The IR8 bit is cleared by writing a 1 to it.
8.5.21.2
Endpoint 9 Interrupt Request (IR9)
The interrupt request bit is set if the IM9 bit in the UDC Interrupt Control Register is
cleared and the OUT packet ready (RPC) or receiver overflow (ROF) in the UDC
Endpoint 9 Control/Status Register or the Isochronous Error Endpoint 9 (IPE9) in the
UFNHR are set.
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
332
®
®
Intel
IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
Interrupt Request Endpoint 7 (read/write 1 to clear).
IR7
1 = Endpoint 7 needs service.
Interrupt Request Endpoint 6 (read/write 1 to clear).
IR6
1 = Endpoint 6 needs service.
Interrupt Request Endpoint 5 (read/write 1 to clear).
IR5
1 = Endpoint 5 needs service.
Interrupt Request Endpoint 4 (read/write 1 to clear).
IR4
1 = Endpoint 4 needs service.
Interrupt Request Endpoint 3 (read/write 1 to clear).
IR3
1 = Endpoint 3 needs service.
Interrupt Request Endpoint 2 (read/write 1 to clear).
IR2
1 = Endpoint 2 needs service.
Interrupt Request Endpoint 1 (read/write 1 to clear).
IR1
1 = Endpoint 1needs service.
Interrupt Request Endpoint 0 (read/write 1 to clear).
IR0
1 = Endpoint 0 needs service.
IXP46X Product Line of Network Processors—USB 1.1 Device
USIR0
0x00000000
Reset Hex Value:
Bits
USIR0
Description
Controller
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
(USIR1)
August 2006
Order Number: 306262-004US
0
0
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