Mvip, Byte Interleaving Two T1 Streams Onto A 4.096-Mbps Backplane; Mvip, Byte Interleaving Four E1 Streams Onto A 8.192-Mbps Backplane Bus - Intel IXP45X Developer's Manual

Figure 181. MVIP, Byte Interleaving Two T1 Streams onto a 4.096-Mbps Backplane
4.096
MHz clock
Frame pulse
6 7 0 1
Bits
Timeslots
31b Xa Xb 0a 0b 1a 1b 2a 2b Xa Xb 3a 3b 4a 4b 5a 5b Xa Xb 6a 6b 7a 7b 8a 8b Xa Xb 9a 9b 10a 10b11a 11b
Unused
timeslots
Frame pulse plus 7 unused bits
13.5.4.3 8.192-Mbps Backplane
This backplane supports 4 E1 or 4 T1 streams on a single line which require that the
interface operates at 8.192 MHz.
Figure 182
occurs at the first byte of the first E1 stream. No unassigned timeslots are necessary
here as the E1 frames can completely fill all the timeslots available.
Figure 182. MVIP, Byte Interleaving Four E1 Streams onto a 8.192-Mbps Backplane Bus
8.192
MHz clock
Frame pulse
6 7 0 1
Bits
Timeslots
31d 0a 0b 0c 0d
When T1 frames are placed on this backplane bus, then unassigned timeslots are
required as a T1 frame is 24 timeslots wide unlike E1, which is 32 timeslots wide.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
746
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Intel IXP45X and Intel
2 3 4 5 6 0
7 x x
illustrates that 4 E1 streams can be byte interleaved. The frame pulse
2 3 4 5 6 0 2 3 4 5 6 7
7 1
1a 1b 1c 1d 2a 2b 2c 2d 3a 3b 3c 3d 4a 4b 4c 4d 5a 5b 5c 5d 6a 6b 6c 6d 7a 7b 7c 7d 8a8b 8c 8d
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IXP46X Product Line of Network Processors—HSS Coprocessor
x x x
x x x x x x x x x x
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6
0 1 2 3 4 5 6 7
Xa
B4252-02
7
9a
B4253-02
August 2006
Reference Number: 004US