Transmit Fifo Service (Tfs); Transmit Packet Complete (Tpc); Flush Tx Fifo (Ftf); Bit 4 Reserved - Intel IXP45X Developer's Manual

8.5.15.1

Transmit FIFO Service (TFS)

The transmit FIFO service bit is be set if one or fewer data packets remain in the
transmit FIFO. UDCCS13[TFS] is cleared when two complete data packets are in the
FIFO. A complete packet of data is signified by loading 256 bytes or by setting
UDCCS13[TSP].
8.5.15.2

Transmit Packet Complete (TPC)

The the UDC sets transmit packet complete bit when an entire packet is sent to the
host. When this bit is set, the IR13 bit in the appropriate UDC status/interrupt register
is set if transmit interrupts are enabled.
This bit can be used to validate the other status/error bits in the Endpoint 13 Control/
Status Register. The UDCCS13[TPC] bit gets cleared by writing a 1 to it. This clears the
interrupt source for the IR13 bit in the appropriate UDC status/interrupt register, but
the IR13 bit must also be cleared.
Setting this bit does not prevent the UDC from transmitting the next buffer. The UDC
issues NAK handshakes to all IN tokens if this bit is set and neither buffer has been
triggered by writing 64 bytes or setting UDCCS13[TSP].
8.5.15.3

Flush Tx FIFO (FTF)

The Flush Tx FIFO bit triggers a reset for the endpoint's transmit FIFO. The Flush Tx
FIFO bit is set when software writes a 1 to it or when the host performs a
SET_CONFIGURATION or SET_INTERFACE.
The bit's read value is zero.
8.5.15.4 Transmit Underrun (TUR)
The transmit underrun bit is be set if the transmit FIFO experiences an underrun. When
the UDC experiences an underrun, UDCCS13[TUR] generates an interrupt.
UDCCS13[TUR] is cleared by writing a 1 to it.
8.5.15.5

Bit 4 Reserved

Bit 4 is reserved for future use.
8.5.15.6

Bit 5 Reserved

Bit 5 is reserved for future use.
8.5.15.7

Bit 6 Reserved

Bit 6 is reserved for future use.
8.5.15.8

Transmit Short Packet (TSP)

Software uses the transmit short packet to indicate that the last byte of a data transfer
has been sent to the FIFO. This indicates to the UDC that a short packet or zero-sized
packet is ready to transmit. Software should always check TSP after loading a packet to
determine if more data can be loaded.
Software must not set this bit, if a packet of 256 bytes is to be transmitted. When the
data packet is successfully transmitted, this bit is cleared by the UDC.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
322
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
August 2006
Order Number: 306262-004US