Pci Byte Enable Generation - Intel IXP45X Developer's Manual

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PCI Controller—Intel IXP45X and Intel
3. The hardware writes the data in PCI_CRP_WDATA to the enabled bytes in the
addressed register of the PCI Core. During this operation, any access of CSR space
from the AHB will be retried.
A burst CSR write operation may be used to write PCI_CRP_AD_CBE and
PCI_CRP_WDATA to initiate the PCI configuration register write operation.
10.3.2.10.5 AHB Non-Prefetch PCI Accesses
The PCI Controller can generate "non-prefetch" (single) PCI cycles such as I/O Read
and Write and Configuration Read and Write cycles from the AHB bus via the non-
prefetch CSRs PCI_NP_AD, PCI_NP_CBE, PCI_NP_WDATA, and PCI_NP_RDATA.
A read access is processed as follows:
1. An AHB master writes the 32-bit address of the PCI read cycle to the PCI_NP_AD
register.
2. The AHB master writes the PCI Command Type and data byte enables for the
desired read cycle to the PCI_NP_CBE register.
3. The hardware sends the read request (address, command, byte enables) to the PCI
Core which performs the indicated read cycle and returns the read data. The data is
loaded into the pci_np_rdata register. While the read operation is pending, any
access of CSR space from the AHB will be retried.
4. The AHB master reads the PCI_NP_RDATA register to retrieve the data. Note that
this AHB read operation can immediately follow the write in step 2. The hardware
will retry the read until the data is valid thus making any data validity handshaking
transparent to software.
A write access is processed as follows:
1. An AHB master writes the 32-bit address of the PCI write cycle to the PCI_NP_AD
register.
2. The AHB master writes the PCI Command Type and data byte enables for the
desired write cycle to the PCI_NP_CBE register. Byte enables conform to the PCI
little-endian convention.
3. The AHB master writes the data to be written to the PCI_NP_WDATA register.
4. The hardware sends the write request (address, command, byte enables, data) to
the PCI Core which performs the indicated write cycle. While the write operation is
in progress, any access of CSR space from the AHB will be retried.
It should be noted that the AHB Slave Interface and CSR hardware do not interpret the
contents of the non-prefetch registers. The address, command, byte enables, and write
data are passed to the PCI Core as-is. Thus, for example, I/O read and write requests
must be set-up such that the byte enables are consistent with the 2 LSBs of the
address in accordance with the PCI Local Bus Specification.
10.3.2.11

PCI Byte Enable Generation

The byte enables for single PCI transactions are generated based on the type of AHB
access (direct read/write or non-prefetch read/write), address, transfer size (8-bit, 16-
bit, 32-bit), and the settings in effect for AHB endianness and data swapping modes. All
32-bit accesses obviously assert all byte enables when the transaction is sent to the
PCI Initiator. Since the AHB Slave Interface only supports bursts with a size of 32-bits,
PCI burst transactions will always have all byte enables asserted.
byte enables for 8-bit and 16-bit single PCI read and write cycles generated by direct
access of the AHB Slave Interface. PCI cycles generated by the non-prefetch CSRs use
the value of the NP_BE field of the PCI_NP_CBE CSR for the byte enables.
August 2006
Order Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel IXP45X and Intel
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IXP46X Product Line of Network Processors
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