Transmitting And Receiving Uart Data - Intel IXP45X Developer's Manual

Intel
Bits 7 and 5 are not implemented by the IXP45X/IXP46X network processors. The use
of bit 7 through bit 4, of the Interrupt Enable Register, is defined differently from the
register definition of standard 16550 UART.
The Interrupt Enable Register is initialized to all zeros after receiving a reset. The
Interrupt Identification Register is a hexadecimal 0x01. Bit 5 and Bit 4 of the Interrupt
Identification Register will always be logic 0.
14.4.5

Transmitting and Receiving UART Data

Transmitting and receiving data using the UARTs for the IXP45X/IXP46X network
processors is accomplished in two modes: Non-FIFO Mode and FIFO Mode.
In Non-FIFO mode, data will be transmitted and received using two registers — the
Transmit-Holding Register (THR) and the Receive-Buffer Register (RBR) — along with
the UART control, status, and interrupt registers.
In FIFO mode, data will be transmitted and received using two 64-entry FIFOs, the
Transmit FIFO, and the Receive FIFO, along with the UART Control, Status, and
Interrupt registers.
The Transmit FIFO is 64 entries deep by 8 bits wide. The Transmit FIFO sizing allows a
complete 8-bit data character to be stored in each entry. When characters smaller than
8 bits are transmitted, they are right-justified.
If a 5-bit character is to be transmitted, the character is represented by a binary
. The value located in the FIFO entry will be hexadecimal 0x16.
10110
The Receive FIFO is 64 entries deep and 11 bits wide. The Receive FIFO sizing allows
for an 8-bit character to be received along with the over-run flag, parity error flag, and
framing error flag for each received character. Smaller characters will be right-justified,
as described for the transmit FIFO.
The error flags position will remain constant, independent of the character size. The
mode of operation and FIFO control parameters will be programmed using the FIFO
Control Register (FCR).
The FIFO Control Register is an 8-bit register that configures the UARTs' mode of
operation. The Transmit and Receive FIFO Enable Bit (TRFIFOE) — Bit 0 of the FIFO
Control Register — determines the UARTs' mode of operation: FIFO Mode or Non-FIFO
Mode. When set to logic 0, the UART will function in Non-FIFO Mode. When set to logic
1, the UART will function in FIFO Mode.
Two bits of the FIFO Control Register are used to reset the Transmit and Receive FIFO:
the Reset Transmit FIFO bit (bit 2 of FCR) and the Reset Receive FIFO (bit 1 of FCR).
Writing logic 0 to these bits has no effect. Writing logic 1 to the Reset Transmit FIFO bit
will cause the Transmit FIFO counter to be reset to 0 and the transmit-data request bit
to be set in the Line-Status Register.
Writing logic 1 to the Reset Receive FIFO bit will cause the Receive FIFO counter to be
reset to 0 and the data ready bit in the Line-Status Register to be cleared. The Overrun
Error Flag, Parity Error Flag, Framing Error Flag, and Break Interrupt Flag in the Line
Status Register will remain unaltered. The Reset Transmit FIFO and Reset Receive FIFO
will be cleared autonomously when the reset has been completed.
The Receive FIFO interrupt trigger level also is set in the FIFO Control Register. The
Receive FIFO interrupt trigger level is used to generate an interrupt when the number
of characters in the Receive FIFO is greater than to or equal to the trigger-level value.
The Interrupt Trigger Level is defined as bit 6 and bit 7 of the FIFO Control Register. The
bit definitions are shown in
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
760
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IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
Table 248.
Receiver-Transmitter (UART)
August 2006
Order Number: 306262-004US