Block Diagram; Detailed Register Descriptions; Hashing Coprocessor: Register Summary; Hashing Unit (Sha) - Intel IXP45X Developer's Manual

Hashing Unit (SHA)—Intel
26.0

Hashing Unit (SHA)

26.1 Overview
The hashing unit (SHA) is used to accelerate digital signature computations and to
whiten the RNG output. It is the responsibility of the Intel XScale
data from the RNG, provide it to the SHA unit, and retrieve the data after it is
complete.
26.2 Feature List
The SHA wrapper supports:
• 32-bit wide data path
• 10 bits of address downstream
• Decode of address bits 3:0 for instruction to the hashing coprocessor
• A busy signal to the AHB/PKE bridge to signal that a hashing process is under way
and cannot take any write or read commands
• An interrupt signal to signal the hashing process is completed
26.3

Block Diagram

26.4

Detailed Register Descriptions

Table 291. Register Legend
Attribute
RV
PR
RS
RW
RW1C
Table 292. Hashing Coprocessor: Register Summary (Sheet 1 of 2)
Block Offset
Register Name
Address Address
0x7000_ 2200
0x7000_ 2204
August 2006
Reference Number: 306262-0014US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Legend
Reserved
Preserved
Read/Set
Read/Write
Normal Read
Write '1' to clear
Hash_Config Hash Configuration Register
Hash_Do Hash Do Register
Attribute Legend
RC Read Clear
RO Read Only
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
Description
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
®
Processor to get the
Page
Reset Value
Number
0x00000000 922
N/A 922
Developer's Manual
Access
RW
WO
921