Timers; Ieee-1588 Hardware Assist; Synchronous Serial Protocol Interface - Intel IXP45X Developer's Manual

Intel
2.1.14

Timers

The IXP45X/IXP46X network processors consist of four internal timers operating at
66.66 MHz to allow task scheduling and prevent software lock-ups. The device has four
32-bit counters:
• Watch-Dog
Timer
The Timestamp Timer and the two general-purpose timers have the optional ability to
use a pre-scaled clock. A programmable pre-scaler can be used to divide the input
clock by a 16-bit value. The input clock can be either the APB clock (66.66 MHz) or a
20-ns version of the APB clock (50 MHz). By default all timers use the APB clock.
The 16-bit pre-scale value ranges from divide by 2 to 65,536 and results in a new clock
enable available for the timers that ranges from 33.33 MHz down to 1,017.26 Hz.
The Timestamp Timer also contains a 32-bit compare register that allows an interrupt
to be created at times other than time 0.
2.1.15

IEEE-1588 Hardware Assist

In a distributed control system containing multiple clocks, individual clocks tend to drift
apart. Some kind of correction mechanism is necessary to synchronize the individual
clocks to maintain global time, which is accurate to some clock resolution. The
IEEE 1588 standard for a precision clock synchronization protocol for networked
measurement and control systems can be used for this purpose.
The IEEE 1588 standard defines several messages that can be used to exchange timing
information. The hardware assist logic required to achieve precision clock
synchronization using the IEEE 1588 standard is left to implementation.
The IXP45X/IXP46X network processors consist of this IEEE 1588 hardware-assist logic
on three of the MII interfaces. Using the hardware assist logic along with software
running on the Intel XScale processor, a full source- or sink-capable IEEE-1588
compliant network node can be implemented.
Note: The Intel
details, see the Intel
Datasheet.
2.1.16

Synchronous Serial Protocol Interface

The IXP45X/IXP46X network processors consist of a dedicated Synchronous Serial
Protocol (SSP) interface. The SSP interface is a full-duplex synchronous serial interface.
It can connect to a variety of external analog-to-digital (A/D) converters, audio and
telecom CODECs, and many other devices which use serial protocols for transferring
data.
It supports National's Microwire*, Texas Instruments' synchronous serial protocol
(SSP), and Motorola's serial peripheral interface (SPI) protocol.
The SSP operates in master mode (the attached peripheral functions as a slave), and
supports serial bit rates from 7.2 Kbps to 1.8432 Mbps using the on-chip, 3.6864-MHz
clock, and bit rates from 64.45 Kbps to 16.5 Kbps using a maximum off-chip, 33-MHz
clock. Serial data formats may range from 4 to 16 bits in length. Two on-chip register
blocks function as independent FIFOs for data, one for each direction. The FIFOs are 16
entries deep x 16 bits wide. Each 32-bit word from the system fills one entry in a FIFO
using the lower half 16-bits of a 32-bit word.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
58
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview
• Timestamp
Timer
®
IXP455 Network Processor does not support IEEE-1588 hardware assist. For
®
IXP45X and Intel
• Two general-purpose timers, read/
writable reload
®
IXP46X Product Line of Network Processors
Reference Number: 306262-004US
August 2006