Exp_Parity_Status; Ex_Addr Value To Access Exp_Lock1 Register - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
Table 237.

EX_ADDR Value to Access EXP_LOCK1 Register

AddrWidth
0x8
0x9
0xA
0xB
12.5.17

EXP_PARITY_STATUS

Register Name:
Physical Address:
Register Description:
Access: See below.
3
1
Register
Bits Name
AHB address[31:2] of the parity error. If multiple parity errors occur,
ErrorAddr contains the address of the first parity error. After receiving
31:2 ErrorAddr
a parity error, the ErrorAddr is locked until InErrorSts and OutErrorSts
are both cleared by software.
A parity error occurred on an inbound write. This bit will never get set
1 InErrorSts
if the PAR_EN bit is not set on EXP_MST_CONTROL register.
A parity error occurred on an outbound read. This bit will not get set
0 OutErrorSts unless PAR_EN is set in the EXP_TIMING_CS for which the parity error
has occurred.
The OR of InErrorSts and OutErrorSts is generated to form exp_parity_error which is
routed to the Interrupt Controller which can generate interrupts to Intel XScale
processor. In the event of multiple inbound parity errors or multiple outbound parity
errors, there is a race condition between when software performs a write to clear the
EXP_PARITY_STATUS register and setting the InErrorSts/OutErrorSts error bit in
hardware. If the software clears the error bit before another parity error of the same
type (i.e Inbound), the EXP_PARITY_STATUS register will be set again. However if
software clears the error bit on or after another parity error, the EXP_PARITY_STATUS
register will be cleared. If the race condition described above is of concern, the best
way to work around this issue is to ensure no other masters are targeting the
Expansion bus controller while software is clearing the EXP_PARITY_STATUS register.
The only way to stop outbound transactions is to have a software mechanism to stop
the originating master from issuing transfers. The easiest mechanism to stop inbound
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network
EX_ADDR[3:0] to read/
write
EXP_INBOUND_ADDR
"11XX"
"11XX"
"11XX"
"11XX"
0xC4000120
Specifies the parity error status.
ErrorAddr
Description
Intel
EX_ADDR[19:4] to read/
write
EXP_INBOUND_ADDR
0x0000
0x0000
0x0000
0x0000
EXP_PARITY_STATUS
Reset Hex Value:
EXP_PARITY_STATUS
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
EX_ADDR[24:20] to read/
write
EXP_INBOUND_ADDR
"10000"
"X1000"
"XX100"
"XXX10"
0x00000000
2 1 0
Reset
Access
Value
0x0 RO
0 RW1C
0 RW1C
Developer's Manual
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