Xmit_Snapshot_High Register (Per Channel) - Intel IXP45X Developer's Manual

Time Synchronization Hardware Assist (TSYNC)—Intel
Line of Network Processors
19.5.2.19

XMIT_Snapshot_High Register (Per Channel)

Register Name:
Block
RegBlockAddress
Base Address:
Transmit Snapshot High Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
When a Sync message in Master mode, or a Delay_Req message in Slave
mode, is transmitted, the current system time is captured in this
XMIT_Snapshot register.
• The XMIT_Snapshot_Low register contains the lower 32 bits of the time
XMIT_
• The XMIT_Snapshot_High register contains the upper 32 bits.
31:0 Snapshot_
After a XMIT_Snapshot has occurred, the txs indication in the
High
TS_Channel_Event register does not clear until the user writes a '1' to that bit
in that register. Therefore, the firmware should read the XMIT_Snapshot_Low
and XMIT_Snapshot_High registers before it writes a '1' to the txs bit to clear
the snapshot indication. In this way, the snapshot value cannot change
between reads of the high and low locations.
August 2006
Order Number: 306262-004US
Offset Address
XMIT_Snapshot_High[31:0]
*Address offsets per channel...
Channel 0 = 0x04C
Channel 1 = 0x06C
Channel 2 = 0x08C
Description
value.
® ®
IXP45X and Intel IXP46X Product
TS_TxSnapHi
0x04C*
TS_TxSnapHi
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
0x0
Reset Value
Access: (See below.)
8 7 6 5 4 3 2
Reset
Access
Value
0
Developer's Manual
1 0
RO
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