Udc Data Register 9 - Intel IXP45X Developer's Manual

USB 1.1 Device Controller—Intel
Processors
Register Name:
0 x C800B700
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 8 Data Register
Description:
Access: Write
31
Bits
31:8
7:0
8.5.39

UDC Data Register 9

Endpoint 9 is a double-buffered, isochronous OUT endpoint that is 256 bytes deep. The
UDC generates an interrupt request when the EOP is received.
Because it is double-buffered, up to two packets of data may be ready. The data can be
removed from the UDC via a direct read from the Intel XScale processor. If one packet
is being removed and the packet behind it has already been received, the UDC issues a
NAK to the host the next time it sends an OUT packet to Endpoint 9.
This NAK condition remains in place until a full packet space is available in the UDC at
Endpoint 9.
Register Name:
0 x C800B900
Hex Offset Address:
Register
Universal Serial Bus Device Endpoint 9 Data Register
Description:
Access: Read
31
Bits
31:8
7:0
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being loaded.
Bits
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
DATA Top of endpoint data currently being read.
Intel
UDDR8
0x00000000
Reset Hex Value:
UDDR8
Description
UDDR9
0x00000000
Reset Hex Value:
UDDR9
Description
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
8 7
(8-Bit Data)
0 0 0 0 0 0 0
(UDDR9)
8 7
(8-Bit Data)
0 0 0 0 0 0 0
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