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Intel

IXP45X and Intel

IXP46X

Product Line of Network Processors

Developer's Manual

August 2006

Order Number: 306262-004US

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Page 1 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 2 Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Page 3: Table Of Contents
® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors Contents Introduction......................38 About This Document..................38 Intended Audience .................... 38 How to Read This Document ................38 Other Relevant Documents ................. 38 Terminology and Conventions ................39 1.5.1...
Page 4 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents Memory Management Unit ..................69 3.1.1 Memory Attributes ..................70 3.1.1.1 Page (P) Attribute Bit..............70 3.1.1.2 Cacheable (C), Bufferable (B), and eXtension (X) Bits ....70 3.1.2 Interaction of the MMU, Instruction Cache, and Data Cache ......72 3.1.3...
Page 5 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.6.4.7 Trace Buffer Enable Bit (E) ............114 3.6.5 Debug Exceptions................. 115 3.6.5.1 Halt Mode ................115 3.6.5.2 Monitor Mode ................. 117 3.6.6 HW Breakpoint Resources..............117 3.6.6.1 Instruction Breakpoints............
Page 6 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 3.7.4.6 Instruction TLB Efficiency Mode ..........165 3.7.4.7 Data TLB Efficiency Mode ............165 3.7.5 Multiple Performance Monitoring Run Statistics ......... 166 3.7.6 Examples..................... 166 Programming Model ..................167 ®...
Page 7 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.10.5.5 Scheduling the MRA and MAR Instructions (MRRC/MCRR) ..... 218 3.10.5.6 Scheduling the MIA and MIAPH Instructions........ 219 3.10.5.7 Scheduling MRS and MSR Instructions ........219 3.10.5.8 Scheduling CP15 Coprocessor Instructions ......... 220 3.10.6 Optimizing C Libraries ................
Page 8 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 6.2.33 Address Mask 3 ..................259 6.2.34 Address Mask 4 ..................259 6.2.35 Address Mask 5 ..................259 6.2.36 Address Mask 6 ..................260 6.2.37 Address Registers ................. 260 6.2.38 Address 1 ....................
Page 9 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.1.4 Resume Interrupt Request (RESIR) ........... 292 8.5.1.5 Suspend Interrupt Request (SUSIR) .......... 292 8.5.1.6 Suspend/Resume Interrupt Mask (SRM)........292 8.5.1.7 Reset Interrupt Request (RSTIR)..........292 8.5.1.8 Reset Interrupt Mask (REM) ............. 292 8.5.2...
Page 10 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 8.5.8 UDC Endpoint 6 Control/Status Register........... 307 8.5.8.1 Transmit FIFO Service (TFS) ............. 307 8.5.8.2 Transmit Packet Complete (TPC) ..........307 8.5.8.3 Flush Tx FIFO (FTF) ..............307 8.5.8.4...
Page 11 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.14.5 Sent Stall (SST)..............320 8.5.14.6 Force Stall (FST)..............320 8.5.14.7 Receive FIFO Not Empty (RNE) ..........320 8.5.14.8 Receive Short Packet (RSP)............321 8.5.15 UDC Endpoint 13 Control/Status Register ..........321 8.5.15.1 Transmit FIFO Service (TFS).............
Page 12 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 8.5.22.5 Start of Frame Interrupt Mask (SIM) .......... 335 8.5.22.6 Start of Frame Interrupt Request (SIR) ........335 8.5.23 UDC Frame Number Low Register ............336 8.5.24 UDC Byte Count Register 2 ..............337 8.5.24.1 Endpoint 2 Byte Count (BC[7:0])..........
Page 13 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.10.3 HWHOST..................... 368 9.10.4 HWDEVICE ..................368 9.10.5 HWTXBUF ................... 369 9.10.6 HWRXBUF ................... 369 9.11 Host Capability Registers.................. 370 9.11.1 CAPLENGTH – EHCI Compliant ............... 370 9.11.2 HCIVERSION – EHCI Compliant .............. 370 9.11.3 HCSPARAMS –...
Page 14 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 9.14.2.2 Port Routing Control via PortOwner and Disconnect Event ..... 413 9.14.2.3 Example Port Routing State Machine .......... 414 9.14.2.4 Port Power ................415 9.14.2.5 Port Reporting Over-Current ............. 415 9.14.3 Suspend/Resume..................
Page 15 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.15.4.3 Port Test Mode ............... 492 9.16 Compatibility ....................493 9.17 Power-Management Requirements..............493 9.17.1 USB Power States ................493 9.17.2 Host Power States ................493 9.18 Error/Abnormal Conditions ................493 10.0 PCI Controller ......................
Page 16 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 10.5 Register Descriptions..................549 10.5.1 PCI Configuration Registers..............549 10.5.2 PCI Configuration Register Descriptions ........... 550 10.5.2.1 Device ID/Vendor ID Register ........... 550 10.5.2.2 Status Register/Control Register..........551 10.5.2.3 Class Code/Revision ID Register ..........
Page 17 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.2.1.2 Address Decode Blocks ............585 11.2.1.3 Memory Transaction Queues ............ 586 11.2.1.4 Configuration Registers............586 11.2.1.5 Refresh Counter ..............586 11.2.1.6 DDRI SDRAM Control Block ............587 11.2.1.7 DDRI SDRAM RCOMP Block ............
Page 18 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 12.4.1.1 Expansion Bus Address Space ........... 653 12.4.1.2 Chip Select Address Allocation........... 653 12.4.1.3 Address and Data Byte Steering ..........655 12.4.1.4 Expansion Bus Interface Configuration ........658 12.4.1.5 Using I/O Wait ................
Page 19 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.5.18EXP_SYNCINTEL_COUNT ............... 722 13.0 HSS Coprocessor ....................723 13.1 Overview ....................... 723 13.1.1 High-Speed Serial Interface Receive Operation ......... 724 13.1.2 High-Speed Serial Interface Transmit Operation ........725 13.2...
Page 20 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 15.0 GPIO Controller ......................776 15.1 Overview ......................776 15.2 Feature List ....................776 15.3 Block Diagram....................776 15.4 Theory of Operation ..................777 15.4.1 Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination..778 15.4.2 Clock Generation ..................
Page 21 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 17.6.5 FIQ Status Register ................814 17.6.6 Interrupt Priority Register..............815 17.6.7 IRQ Highest-Priority Register ..............815 17.6.8 FIQ Highest-Priority Register..............816 17.6.9 Error High Priority Enable Register ............816 18.0 Operating System Timer ..................
Page 22 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 19.5.2.1 Time Sync Control Register............839 19.5.2.2 Time Sync Event Register ............840 19.5.2.3 Addend Register..............840 19.5.2.4 Accumulator Register ............... 841 19.5.2.5 Test Register ................842 19.5.2.6 RawSystemTime_Low Register ..........843 19.5.2.7 RawSystemTime_High Register ..........
Page 23 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 20.5.3.4 Transmit FIFO Service Request Flag (TFS) (Read-Only, Maskable Interrupt)..........870 20.5.3.5 Receive FIFO Service Request Flag (RFS) (Read-Only, Maskable Interrupt)..........870 20.5.3.6 Receiver Overrun Status (ROR) ..........870 20.5.3.7 Transmit FIFO Level (TFL) ............
Page 24 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 23.4 Theory of Operation ..................908 23.4.1 Peripheral Information................908 24.0 Random Number Generator ..................911 24.1 Theory of Operation ..................911 24.2 Detailed Register Descriptions ................911 24.2.1 Registers ..................... 912 24.2.1.1 Random Number FIFO..............
Page 25 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 27.6.5 Queues 32-63 Nearly Empty Status Register ..........941 27.6.6 Queues 32-63 Nearly Full Status Register ..........942 27.6.7 Queues 32-63 Full Status Register ............942 27.6.8 Interrupt 0 Status Flag Source Select Register 0 – 3 ......... 942 27.6.9 Queue Interrupt Enable Register 0 –...
Page 26 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents LDIC JTAG Data Register Hardware ................140 Format of LDIC Cache Functions ................142 Code Download During a Cold Reset For Debug ............144 Code Download During a Warm Reset For Debug ............146 Downloading Code in IC During Program Execution .............
Page 27 116 DDRI SDRAM Pipelined Writes.................. 612 117 Refresh While the Memory Bus is Not Busy ..............613 118 ECC Write Flow ...................... 615 119 IXP45X/IXP46X product line G-Matrix (Generates the ECC) .......... 617 120 Sub 64-bit DDRI SDRAM Write (D ) ................619 121 ECC Read Data Flow ....................
Page 28 Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 129 Expansion Bus Write (Intel, Multiplexed Mode) ............666 130 Expansion Bus Read (Intel, Multiplexed Mode)............667 131 Expansion Bus Write (Intel Simplex-Mode, Synchronous Intel)........668 132 Expansion Bus Read (Intel Simplex-Mode) ..............669 133 Intel Synchronous 8-Word Read ................
Page 29 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 184 UART Block Diagram....................752 185 GPIO Block Diagram ....................777 186 Interrupt Controller Block Diagram ................806 187 Operating System Timer Block Diagram ..............818 188 Block Diagram of TSync Circuit ................831 189 Time Stamp Reference Point..................
Page 30 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents Accessing Process ID ....................106 Process ID Register....................106 Accessing the Debug Registers ................. 107 Coprocessor Access Register ..................108 CP14 Registers....................... 109 Accessing the Performance Monitoring Registers ............109 PWRMODE Register....................
Page 31 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors Latency Example....................184 Branch Instruction Timings (Those Predicted by the BTB) ..........184 Branch Instruction Timings (Those not Predicted by the BTB)........184 Data Processing Instruction Timings ................. 184 Multiply Instruction Timings..................
Page 32 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 135 USBSTS – USB Status ..................... 376 136 USBINTR – USB Interrupt Enable ................377 137 FRINDEX – USB Frame Index ................... 379 138 PERIODICLISTBASE - Host Controller Frame List Base Address ........380 139 ASYNCLISTADDR - Host Controller Next Asynchronous Address ........
Page 33 217 Example Expansion Bus Pin Mappings to Target Devices ..........651 218 Supported AHB Commands..................652 219 Trimmed Version of IXP45X/IXP46X network processors Memory Map ......653 220 Expansion Bus Address and Data Byte Steering............656 221 Multiplexed Output Pins for HPI Operation ..............664 222 HPI HCNTL Control Signal Decoding................
Page 34 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Contents 244 Typical Baud-Rate Settings ..................753 245 UART Transmit Parity Operation ................755 246 UART Receive Parity Operation ................. 755 247 UART Word-Length Select Configuration ..............755 248 UART FIFO Trigger Level..................761 249 Register Legend .....................
Page 35 ® ® Contents—Intel IXP45X and Intel IXP46X Product Line of Network Processors 299 NPE Coprocessor Response..................955 300 NPE Reset State..................... 956 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual Order Number: 306262-004US...
Page 36: Revision History
21.5.1: Added note to clarify SCL operation (CCR2002036) Removed SS-SMII references since this feature is not supported (CCR1980266) ® Updated ‘Intel® XScale Core’ references to be ‘Intel XScale Processor’. Only the terminology used in the document has changed. Incorporated specification changes, specification clarifications and document ®...
Page 37 ® ® Revision History—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual Order Number: 306262-004US...
Page 38: Introduction
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction Introduction About This Document This document is the authoritative and definitive reference for the external architecture ® ® of the Intel IXP45X and Intel IXP46X Product Line of Network Processors based on ®...
Page 39: Terminology And Conventions
® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors Terminology and Conventions This section explains the naming conventions and the terminology used in the document. Common acronyms are defined in Table Table 1. List of Acronyms (Sheet 1 of 4)
Page 40 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction Table 1. List of Acronyms (Sheet 2 of 4) Acronym Description GBps Gigabytes per second Gbps Gigabits per second General Circuit Interface GPIO General-Purpose Input/Output HDLC High-Level Data Link Control...
Page 41 ® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 1. List of Acronyms (Sheet 3 of 4) Acronym Description Message Digest 5 MDIO Management Data Input/Output MFAS Multiframe Alignment Signals Maximum Frame Size Management Information Base...
Page 42: Number Representation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Introduction Table 1. List of Acronyms (Sheet 4 of 4) Acronym Description SNMP Simple Network Management Protocol Start-of-Frame SPHY Single PHY SRAM Static Random Access Memory SSRAM Synchronous Static Random Access Memory...
Page 43: Register Legend
® ® Introduction—Intel IXP45X and Intel IXP46X Product Line of Network Processors 1.5.3 Register Legend In this document, the following register access definitions are used: Table 2. Register Legend Attribute Legend Attribute Legend Reserved Read Clear Preserved Read Only Read/Set...
Page 44: Functional Overview
RISC ISA, the ability to simultaneously process data with up to three integrated network processing engines (NPEs), and numerous dedicated-function peripheral interfaces — enables the IXP45X/IXP46X network processors to operate over a wide range of low-cost networking applications with industry-leading performance.
Page 45: Ixp465 Network Processor Block Diagram
® ® Functional Overview—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® Figure 1. Intel IXP465 Network Processor Block Diagram HSS 0 HSS 1 NPE A UTOPIA 2/MII/SMII MII / SMII NPE B NPE C North AHB 133.32 MHz x 32 bits...
Page 46: Ixp460 Network Processor Block Diagram
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview ® Figure 2. Intel IXP460 Network Processor Block Diagram MII/SMII NPE B North AHB 133MHz x 32 bits MII/SMII NPE C North AHB Arbiter IEEE 1588 Public Key...
Page 47: Ixp455 Network Processor Block Diagram
® ® Functional Overview—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® Figure 3. Intel IXP455 Network Processor Block Diagram HSS 0 HSS 1 NPE A UTOPIA 2/MII/SMII MII/SMII NPE B NPE C North AHB 133.32 MHz x 32 bits...
Page 48: Key Functional Units
The NPE core is a hardware multi-threaded processor engine separate from, but operating in parallel with the Intel XScale processor. The NPE is used to off-load and accelerate network data packet processing that would otherwise take processing cycle time on the Intel XScale processor. Each NPE core is a 133.32-MHz processor core that has self-contained instruction memory and self-contained data memory that operate in parallel.
Page 49: Internal Bus
The combined forces of the hardware multi-threading, independent instruction memory, independent data memory, and parallel processing — contained on the NPE — allows the Intel XScale processor to be utilized for application purposes. The multi- processing capability of the peripheral interface functions allows unparalleled performance to be achieved by the application running on the Intel XScale processor.
Page 50: South Ahb
South AHB ® The South AHB is a 133.32-MHz, 32-bit bus that can be mastered by the Intel XScale Processor, PCI controller, Expansion Bus Interface, USB Host Controller, and the AHB/ AHB bridge. The targets of the South AHB Bus can be the DDRI SDRAM, PCI Controller, Queue Manager, Expansion Bus, Cryptography Unit, or the AHB/APB bridge.
Page 51: Apb Bus
No arbitration is required due to a single master implementation. 2.1.3 MII/SMII Interfaces The IXP45X/IXP46X network processors can be configured to support up to three MII or SMII industry-standard, media-independent interface (MII) interfaces. These interfaces are integrated into the IXP45X/IXP46X network processors with separate media-access controllers and in many cases independent network processing engines.
Page 52: Universal Serial Bus (Usb) Interfaces
When the PCI Controller is configured as a host, an internal PCI arbiter may be utilized to allow up to four devices to be connected to the IXP45X/IXP46X network processors without the need for an external arbiter.
Page 53: Ddri Sdram Controller
It is important to note that ECC is also referred to as CB in many DIMM specs. The pins used for ECC on the IXP45X/IXP46X network processors are called DDRI_CB[7:0]. The controller supports the 8 bits due to the fact that internally it is a 32 or 64 bit controller.
Page 54: Expansion Interface
The memory controller is a 32-bit only interface. If a x16 memory chip is used, a minimum of two memory chips would be required to facilitate the 32-bit interface required by the IXP45X/IXP46X network processors. If ECC is required, additional memories would need to be added. For more information on DDRI SDRAM support and configuration see the Memory Controller section contained later in this document.
Page 55 In the enhanced mode of operation, the expansion interface is a 32-bit interface that allows an address range of 512 bytes to 32 Mbytes per chip select on the IXP45X/ IXP46X network processors, using 25 address lines for each of the eight independent chip selects.
Page 56: High-Speed, Serial Interfaces
High-Speed, Serial Interfaces The high-speed, serial interfaces (HSS) are six-signal interfaces that support serial transfer speeds from 512 KHz to 8.192 MHz, for some models of the IXP45X/IXP46X network processors. (For processor-specific speeds, refer to the HSS chapter.) Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs to the IXP45X/IXP46X network processors.
Page 57: Internal Bus Performance Monitoring Unit (Ibpmu)
Internal Bus Performance Monitoring Unit (IBPMU) The IXP45X/IXP46X network processors consist of a performance monitoring unit that may be used to capture predefined events within the system outside of the Intel XScale processor. These features aid in measuring and monitoring various system parameters that contribute to the overall performance of the processor.
Page 58: Timers
IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview 2.1.14 Timers The IXP45X/IXP46X network processors consist of four internal timers operating at 66.66 MHz to allow task scheduling and prevent software lock-ups. The device has four 32-bit counters: • Watch-Dog •...
Page 59: I2C Interface
IXP46X Product Line of Network Processors 2.1.17 C Interface The I C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a master and slave device residing on the I C bus. The I C bus is a serial bus consisting of a two-pin interface.
Page 60: Queue Manager
The Queue Manager interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale processor (or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE condition select logic), and two interrupts to the Intel XScale processor.
Page 61 • Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale processor only. An additional PMU is supplied for monitoring of internal bus performance.
Page 62: Super Pipeline
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview ® Figure 4. Intel XScale Processor Block Diagram Branch Target Cache Interrupt Request Instruction Cache Instruction 32Kb South Execution Core Data Cache Data 32Kb Address Coprocessor Interface...
Page 63: Branch Target Buffer
® ® Functional Overview—Intel IXP45X and Intel IXP46X Product Line of Network Processors • The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift) . . . then finish with the following MAC stages • MAC 1 •...
Page 64: Data Memory Management Unit
Access permissions for each of up to 16 memory domains can be programmed. When a data fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a data abort is sent to the Intel XScale processor for exception processing.
Page 65: Data Cache
The FB can contain up to four unique “miss” addresses (logical), allowing four “misses” before the Intel XScale processor is stalled. The PB holds up to four addresses (logical) for additional “misses” to those addresses that are already in the FB. A coprocessor register can specify draining of the fill and pend (write) buffers.
Page 66: Write Buffer
The write buffer (WB) holds data for storage to memory until the bus controller can act on it. The WB is eight entries deep, where each entry holds 16 bytes. The WB is constantly enabled and accepts data from the Intel XScale processor, D-cache, or mini- data cache.
Page 67: Debug Unit
The debug unit — when used with debugger application code running on a host system outside of the Intel XScale processor — allows a program, running on the Intel XScale processor, to be debugged. It allows the debugger application code or a debug exception to stop program execution and redirect execution to a debug-handling routine.
Page 68 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Functional Overview ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Reference Number: 306262-004US...
Page 69: Intel Xscale ® Processor
These translations can also be locked down in either TLB to guarantee the performance of critical routines. For more information, refer to “Exceptions” on page The Intel XScale processor allows system software to associate various attributes with regions of memory: • Cacheable • Bufferable •...
Page 70: Memory Attributes
• When the bit is 1, the type of coherency performed is dependent on the P-Attribute bit. The P-Attribute bit is associated with each 1-Mbyte page. The P-Attribute bit is output from the Intel XScale processor with any store or load access associated with that page. Note: The P-attribute feature allows software to control byte swapping per 1-Mbyte regions.
Page 71: Data Cache And Buffer Behavior When X = 0
All of these descriptor bits affect the behavior of the Data Cache and the Write Buffer. ® If the X bit for a descriptor is zero, the C and B bits operate as mandated by the Intel StrongARM architecture, refer to the ARM* Architecture Reference Manual. This...
Page 72: Interaction Of The Mmu, Instruction Cache, And Data Cache
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Table 6. Data Cache and Buffer Behavior When X = 1 Line Cacheable Bufferable Write Policy Allocation Notes Policy Unpredictable -- do not use Writes will not coalesce into buffers...
Page 73: Mmu Control
TLB can also be invalidated. See Table 21, “TLB Functions” on page 105 a listing of commands supported by the Intel XScale processor. Globally invalidating a TLB will not affect locked TLB entries. However, the invalidate- entry operations can invalidate individual locked entries. In this case, the locked contents remain in the TLB, but will never “hit”...
Page 74: Locking Entries
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Example 1. Enabling the MMU ; This routine provides software with a predictable way of enabling the MMU. ; After the CPWAIT, the MMU is guaranteed to be enabled. Be aware ;...
Page 75 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Example 2. Locking Entries into the Instruction TLB ; R1, R2 and R3 contain the virtual addresses to translate and lock into ; the instruction TLB.
Page 76: Round-Robin Replacement Algorithm
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Example 3. Locking Entries into the Data TLB ; R1, and R2 contain the virtual addresses to translate and lock into the data TLB P15,0,R1,C8,C6,1 ;...
Page 77: Instruction Cache
B4326-01 Instruction Cache The Intel XScale processor instruction cache enhances performance by reducing the number of instruction fetches from external memory. The cache provides fast execution of cached code. Code can also be locked down when guaranteed or fast access time is required.
Page 78: Instruction-Cache 'Miss
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor memory that contains the requested instruction using the fetch policy described in “Instruction-Cache ‘Miss’” on page 78. As the fetch returns instructions to the cache, the instructions are placed in one of two fetch buffers and the requested instruction is delivered to the instruction decoder.
Page 79: Instruction-Cache Line-Replacement Algorithm
1 word per core cycle. The instruction cache can have the eight words of data return in any order, which allows the Intel XScale processor to send the requested instruction first, thus reducing fetch latency. (This is referred to as critical word first.)As each word returns, the corresponding valid bit is set for the word in the...
Page 80: Instruction-Cache Coherence
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Example 4. Recovering from an Instruction Cache Parity Error ; Prefetch abort handler MCR P15,0,R0,C7,C5,0 ; Invalidate the instruction cache and branch target ; buffer CPWAIT ;...
Page 81 ; The instruction cache is guaranteed to be invalidated at this point; the next ; instruction sees the result of the invalidate command. The Intel XScale processor also supports invalidating an individual line from the instruction cache. See Table 20, “Cache Functions” on page 104 for the exact command.
Page 82: Locked Line Effect On Round-Robin Replacement
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor • The code being locked into the cache must be cacheable • The instruction cache must be enabled and invalidated prior to locking down lines. Failure to follow these requirements will produce unpredictable results when accessing the instruction cache.
Page 83: Branch Target Buffer
; if not done, do the next line The Intel XScale processor provides a global unlock command for the instruction cache. Writing to coprocessor 15, register 9 unlocks all the locked lines in the instruction cache and leaves them valid. These lines then become available for the round-robin replacement algorithm.
Page 84: Btb Entry
Thumb execution. This organization means that two consecutive Thumb branch (B) instructions, with instruction address bits[8:2] the same, will contend for the same BTB ® entry. Thumb also requires 31 bits for the branch target address. In Intel StrongARM mode, bit[1] is zero.
Page 85: Reset
There are two data cache structures in the Intel XScale processor: a 32-Kbyte data cache and a 2-Kbyte mini-data cache. An eight entry write buffer and a four-entry, fill buffer are also implemented to decouple the Intel XScale processor instruction execution from external memory accesses, which increases overall system performance.
Page 86: Data Cache Organization
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor The data cache is virtually addressed and virtually tagged. The data cache supports write-back and write-through caching policies. The data cache always allocates a line in the cache when a cacheable read miss occurs and will allocate a line into the cache on a cacheable write miss when write allocate is specified by its page attribute.
Page 87: Mini-Data Cache Organization
The fill buffer holds the external memory request information for a data cache or mini- data cache fill or non-cacheable read request. Up to four 32-byte read request operations can be outstanding in the fill buffer before the Intel XScale processor needs to stall.
Page 88: Cacheability
If there is no outstanding fill request for that line, the current load request is placed in the fill buffer and a 32-byte external memory read request is made. If the pending buffer or fill buffer is full, the Intel XScale processor will stall until an entry is available.
Page 89 If there is no outstanding fill request for that line, the current store request is placed in the fill buffer and a 32-byte external memory read request is made. If the pending buffer or fill buffer is full, the Intel XScale processor will stall until an entry is available.
Page 90 ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor data cache is to cache data that exhibits low temporal locality, i.e.,data that is placed into the mini-data cache is typically modified once and then written back out to external memory.
Page 91 ® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors This same register also provides the command to invalidate the entire data cache and mini-data cache. Refer to Table 20, “Cache Functions” on page 104 for a listing of the commands.
Page 92: Reconfiguring The Data Cache As Data Ram
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor The time it takes to execute a global clean operation depends on the number of dirty lines in cache. 3.4.3 Reconfiguring the Data Cache as Data RAM Software has the ability to lock tags associated with 32-byte lines in the data cache, thus creating the appearance of data RAM.
Page 93 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Example 10. Locking Data into Data Cache ; R1 contains the virtual address of a region of memory to lock, ; configured with C=1 and B=1 ;...
Page 94 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Example 11. Creating Data RAM ; R1 contains the virtual address of a region of memory to configure as data RAM, ; which is aligned on a 32-byte boundary.
Page 95: Locked Line Effect On Round-Robin Replacement
Before locking, the programmer must ensure that no part of the target data range is already resident in the cache. The Intel XScale processor will not prefetch such data, which will result in it not being locked into the cache. If there is any doubt as to the location of the targeted memory data, the cache should be cleaned and invalidated to prevent this scenario.
Page 96: Configuration
VAs, while privileged code that programs CP15 occasionally needs to use MVAs. The format of MRC and MCR is shown in Table cp_num is defined for CP15, CP14 and CP0 on the Intel XScale processor. CP0 supports instructions specific for DSP and is described in “Programming Model” on page 167 Unless otherwise noted, unused bits in coprocessor registers have unpredictable values when read.
Page 97: Mrc/Mcr Format
® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 9. MRC/MCR Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 98: Cp15 Registers
CP13. Access to unimplemented coprocessors (as defined by the cpConfig bus) cause exceptions. 8-bit word offset 3.5.1 CP15 Registers Table 11 lists the CP15 registers implemented in the IXP45X/IXP46X network processors. Table 11. CP15 Registers Register Opcode_2 Access Description...
Page 99: Id Register
Read / Write Ignored Differences may include errata that dictate different operating conditions, software work-around, etc. Value returned will be 000b Product Number for:IXP45X/IXP46X network processors Read / Write Ignored 100000b Product Revision for:IXP45X/IXP46X network processors Read / Write Ignored...
Page 100: Register 1: Control And Auxiliary Control Registers
Register 1 is made up of two registers, one that is compliant with Intel StrongARM Version 5TE and referred by opcode_2 = 0x0, and the other which is specific to the Intel XScale processor is referred by opcode_2 = 0x1. The latter is known as the Auxiliary Control Register. ®...
Page 101: Auxiliary Control Register
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® Table 14. Intel StrongARM Control Register (Sheet 2 of 2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 102: Register 2: Translation Table Base Register
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor 3.5.1.3 Register 2: Translation Table Base Register Table 16. Translation Table Base Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 103: Register 6: Fault Address Register
The Drain Write Buffer function not only drains the write buffer but also drains the fill buffer. The Intel XScale processor does not check permissions on addresses supplied for cache or TLB functions. Due to the fact only privileged software may execute these functions, full accessibility is assumed.
Page 104: Register 8: Tlb Operations
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Disabling/enabling a cache has no effect on contents of the cache: valid data stays valid, locked items remain locked. All operations defined in Table 20 work regardless of whether the cache is enabled or disabled.
Page 105: Register 9: Cache Lock Down
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors This register should be accessed as write-only. Reads from this register, as with an MRC, have an undefined effect. Table 21. TLB Functions Function opcode_2...
Page 106: Register 10: Tlb Lock Down
4 Gbytes of address space. If bits 31:25 are not zero, no remapping occurs. This feature is useful for operating system management of processes that may map to the same virtual address space. In those cases, the virtually mapped caches on the Intel XScale processor would not require invalidating on a process switch.
Page 107: The Pid Register Affect On Addresses
(IBCR0 and IBCR1), one data breakpoint address register (DBR0), one configurable data mask/address register (DBR1), and one data breakpoint control register (DBCON). The Intel XScale processor also supports a 256-entry, trace buffer that records program execution information. The registers to control the trace buffer are located in CP14.
Page 108: Cp14 Registers
1 = Access allowed. Includes read and write accesses. 3.5.2 CP14 Registers Table 29 lists the CP14 registers implemented in the Intel XScale processor. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual...
Page 109: Performance Monitoring Registers
Write: MCR p14, 0, Rd, c3, c2, 0 3.5.2.2 Clock and Power Management Registers These registers contain functions for managing the core clock and power. For the IXP45X/IXP46X network processors, these registers are not implemented and reserved for future use. ® ®...
Page 110: Software Debug Registers
Read-unpredictable / Write-as-Zero Reserved Mode (M) Read / Write 0 = ACTIVE Never change from 00b The Intel XScale processor clock frequency cannot be changed by software on the IXP45X/IXP46X network processors. Table 32. Clock and Power Management Function Data...
Page 111: Software Debug
• Debug Handler SW requirements and suggestions 3.6.1 Definitions Debug handler: Debug handler is event handler that runs on the IXP45X/IXP46X network processors, when a debug event occurs. Debugger: The debugger is software that runs on a host system outside of the IXP45X/IXP46X network processors.
Page 112: Debug Modes
When the debug unit is configured for halt mode, the reset vector is overloaded to serve as the debug vector. A new processor mode, DEBUG mode (CPSR[4:0] = 0x15), ® is added to allow debug exceptions to be handled similarly to other types of Intel StrongARM exceptions.
Page 113 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 35. Debug Control and Status Register (DCSR) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10...
Page 114: Global Enable Bit (Ge)
A debug exception is generated before the instruction in the exception vector executes. Software running on the IXP45X/IXP46X network processors must set the Global Enable bit and the debugger must set the Halt Mode bit and the appropriate vector trap bit through JTAG to set up a non-reset vector trap.
Page 115: Debug Exceptions
ICache” on page 139 for details about downloading code into the instruction cache. During Halt mode, software running on the IXP45X/IXP46X network processors cannot access DCSR, or any of hardware breakpoint registers, unless the processor is in Special Debug State (SDS), described below.
Page 116 ® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor • Disables the trace buffer • Sets DCSR.moe encoding • Processor enters a Special Debug State (SDS) • For data breakpoints, trace buffer full break, and external debug break:...
Page 117: Monitor Mode
3.6.5.2 Monitor Mode ® In monitor mode, the processor handles debug exceptions like normal Intel StrongARM exceptions. If debug functionality is enabled (DCSR[31] = 1) and the processor is in Monitor mode, debug exceptions cause either a data abort or a pre-fetch abort.
Page 118: Instruction Breakpoints
(either on the host or by the debug handler). 3.6.6.2 Data Breakpoints The debug architecture of the IXP45X/IXP46X network processors defines two data breakpoint registers (DBR0, DBR1). The format of the registers is shown in Table Table 38.
Page 119: Data Breakpoint Controls Register (Dbcon)
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors DBR0 is a dedicated data address breakpoint register. DBR1 can be programmed for one of two operations: • Data address mask • Second data address breakpoint The DBCON register controls the functionality of DBR1, as well as the enables for both DBRs.
Page 120: Software Breakpoints
® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor When a memory access triggers a data breakpoint, the breakpoint is reported after the access is issued. The memory access will not be aborted by the processor. The actual timing of when the access completes with respect to the start of the debug handler depends on the memory configuration.
Page 121: Rx Register Ready Bit (Rr)
® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 40. TX RX Control Register (TXRXCTRL) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 122: Overflow Flag (Ov)
Table 42. High-Speed Download Handshaking States Debugger Actions • Debugger wants to transfer code into the IXP45X/IXP46X network processors ’ system memory. • Prior to starting download, the debugger must polls RR bit until it is clear. Once the RR bit is clear, indicating the debug handler is ready, the debugger starts the download.
Page 123: Tx Register Ready Bit (Tr)
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.6.8.4 TX Register Ready Bit (TR) The debugger and debug handler use the TR bit to synchronize accesses to the TX register. The debugger and debug handler must poll the TR bit before accessing the TX register.
Page 124: Transmit Register
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor 3.6.9 Transmit Register The TX register is the debug handler transmit buffer. The debug handler sends data to the debugger through this register. Table 45.
Page 125: Seldcsr Jtag Command
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.6.11.1 SELDCSR JTAG Command The ‘SELDCSR’ JTAG instruction selects the DCSR JTAG data register. The JTAG op code is ‘01001’. When the SELDCSR JTAG instruction is in the JTAG instruction register, the debugger can directly access the Debug Control and Status Register (DCSR).
Page 126: Seldcsr Data Register
“Debug Control and Status Register (DCSR)” on page 113 are updated. An external host and the debug handler running on the IXP45X/IXP46X network processors must synchronize access the DCSR. If one side writes the DCSR at the same side the other side reads the DCSR, the results are unpredictable.
Page 127: Dbgtx Jtag Command
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors DBG.HLD_RST can only be cleared by scanning in a ‘0’ to DBG_SR[1] and scanning in the appropriate values for the DCSR and DBG.BRK. 3.6.11.2.2 DBG.BRK DBG.BRK allows the debugger to generate an external debug break and...
Page 128: Dbgrx Jtag Command
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Figure 15. DBGTX Hardware software write set by SW write to TX software read-only TXRXCTRL Core CLK 0x0000 0000 TCLK Capture_DR delay clear by Debugger read...
Page 129: Dbgrx Hardware
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 16. DBGRX Hardware software read/write undefined delay Capture_DR TXRXCTRL DBG_SR DBG_REG[1] Update_DR clear by SW read from RX set by Debugger Write DBG_REG clear DBG_REG[34]...
Page 130: Rx Write Logic
® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor and sets DBG_REG[34] to signal the data is valid. Since DBG_REG[34] is never cleared by the debugger in this case, the ‘0’ to ‘1’ transition used to enable the debugger write to RX would not occur.
Page 131: Dbgrx Data Register
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 18. DBGRX Data Register TXRXCTRL[31] Capture_DR DBG_SR DBG.RR cleared by RX Write Logic Update_DR DBG_REG DBG.FLUSH DBG.D DBG.RX DBG.V B4344-01 3.6.11.6.3 DBG.RR The debugger uses DBG.RR as part of the synchronization that occurs between the debugger and debug handler for accessing RX.
Page 132: Debug Jtag Data Register Reset Values
DBG.D is provided for use during high speed download. This bit is written directly to TXRXCTRL[29]. The debugger sets DBG.D when downloading a block of code or data to the system memory of the IXP45X/IXP46X network processors. The debug handler then uses TXRXCTRL[29] as a branch flag to determine the end of the loop.
Page 133: Cp 14 Trace Buffer Register Summary
31:0 Read/Write target address for corresponding entry in trace buffer The two checkpoint registers (CHKPT0, CHKPT1) on the IXP45X/IXP46X network processors provide the debugger with two reference addresses to use for re- constructing the trace history. When the trace buffer is enabled, reading and writing to either checkpoint register has unpredictable results.
Page 134: Trace Buffer Entries
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor 3.6.12.1.2 Trace Buffer Register (TBREG) The trace buffer is read through TBREG, using MRC and MCR. Software should only read the trace buffer when it is disabled. Reading the trace buffer while it is enabled, may cause unpredictable behavior of the trace buffer.
Page 135: Message Byte Formats
THUMB bl, b. ® ® Indirect branches include Intel StrongARM ldm, ldr, and dproc to PC; Intel StrongARM THUMB bx, blx(1) and blx(2); and THUMB pop. 3.6.13.1.1 Exception Message Byte When any kind of exception occurs, an exception message is placed in the trace buffer.
Page 136 ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor of the instruction not matching the CC flags. In the case of back-to-back branches the word count would be 0 indicating that no instructions executed after the last branch and before the current one.
Page 137: Trace Buffer Usage
3.6.13.2 Trace Buffer Usage The trace buffer for the IXP45X/IXP46X network processors is 256 bytes in length. The first byte read from the buffer represents the oldest trace history information in the buffer. The last (256th) byte read represents the most recent entry in the buffer. The last byte read from the buffer will always be a message byte.
Page 138 ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor The trace buffer must be initialized prior to its initial usage, then again prior to each subsequent usage. Initialization is done be reading the entire trace buffer. The process...
Page 139: Downloading Code In Icache
3.6.14 Downloading Code in ICache On the IXP45X/IXP46X network processors, a 2-K mini instruction cache — physically separate from the 32-K main instruction cache — can be used as an on-chip instruction RAM. An external host can download code directly into either instruction cache through JTAG.
Page 140: Ldic Jtag Data Register
Shift_DR state. Update_DR parallel loads LDIC_SR1 into LDIC_REG which is then synchronized with the IXP45X/IXP46X network processors’ clock and loaded into the LDIC_SR2. Once data is loaded into LDIC_SR2, the LDIC State Machine turns on and serially shifts the contents if LDIC_SR2 to the instruction cache.
Page 141: Ldic Cache Functions
The LDIC Invalidate Mini IC function does not invalidate the BTB (like the CP15 Invalidate IC function) so software must do this manually where appropriate. ® Load Main IC and Load Mini IC write one line of data (eight Intel StrongARM instructions) into the specified instruction cache at the specified virtual address.
Page 142: Loading Ic During Reset
For functions that require an address, bits[32:6] of the first packet specify an eight-word aligned address (Packet1[32:6] = VA[31:5]). For Load Main IC and Load ® Mini IC, eight additional data packets are used to specify eight Intel StrongARM instructions to be loaded into the target instruction cache. Bits[31:0] of the data packets contain the data to download.
Page 143 ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors • HALT mode — Active when the Halt Mode bit is set in the DCSR; prevents only the mini instruction cache from being invalidated; main instruction cache is invalidated by reset.
Page 144: Code Download During A Cold Reset For Debug
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Figure 24. Code Download During a Cold Reset For Debug RESET pin asserted until hold_rst signal is set Reset Pin TRST resets JTAG IR to IDCODE...
Page 145 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors An additional issue for debug is setting up the reset vector trap. This must be done before the internal reset signal is de-asserted. As described in “Vector Trap Bits...
Page 146: Code Download During A Warm Reset For Debug
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Figure 25. Code Download During a Warm Reset For Debug RESET pin asserted until hold_rst signal is set Reset pin TRST RESET does not affect Mini IC (Halt Mode Bit set)
Page 147: Dynamically Loading Ic After Reset
An external host can load code into the instruction cache “on the fly” or “dynamically.” This occurs when the host downloads code while the processor is not being reset. However, this requires strict synchronization between the code running on the IXP45X/ IXP46X network processors and the external host. The guidelines for downloading code during program execution must be followed to ensure proper operation of the processor.
Page 148 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor that line. Failure to invalidate a line prior to writing it may cause unpredictable operation by the processor. • When the host completes its download, the host must wait a minimum of 15 TCKs, then switch the JTAG IR to DBGRX, and complete the handshaking (by scanning in a value that sets DBG_SR[35]).
Page 149: Debug-Handler Code To Implement Synchronization During Dynamic Code Download
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 53. Debug-Handler Code to Implement Synchronization During Dynamic Code Download # Before the download can start, all outstanding instruction fetches must complete. # The MCR invalidate IC by line function serves as a barrier instruction in # the core.
Page 150: Mini-Instruction Cache Overview
This section describes the overall debug process in Halt Mode. It describes how to start and end a debug session and details for implementing a debug handler. Intel provides a standard Debug Handler that implements some of the techniques in this section. The Intel Debug Handler itself is a a document describing additional handler implementation techniques and requirements.
Page 151 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors to perform any necessary initialization. The reset vector trap is the only debug exception that can occur with debug globally disabled (DCSR[31]=0). Therefore, the debugger must also enable debug prior to existing the handler to ensure all subsequent debug exceptions correctly break to the debug handler.
Page 152: Implementing A Debug Handler
Intel provides a standard debug handler and API which can be used by third-party vendors. Issues and details for writing a debug handler are discussed in this section and in the Intel Debug Handler. 3.6.15.2.1...
Page 153 3.6.15.2.3 Dynamic Debug Handler On the IXP45X/IXP46X network processors, the debug handler and override vector tables reside in the 2-KByte, mini instruction cache, separate from the main instruction cache. A “static” Debug Handler is downloaded during reset. This is the base handler code, necessary to do common operations such as handler entry/exit, parse commands ®...
Page 154 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor If the dynamic function is already downloaded in the main instruction cache, the debugger immediately downloads the address, signalling the handler to continue. The static Debug Handler only needs to support one dynamic function command.
Page 155: Ending A Debug Session
® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors The download bit acts as a branch flag, signalling to the handler to continue with the download. This removes the need for a counter in the debug handler.
Page 156: Software Debug Notes And Errata
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor These actions ensure that the application program executes correctly after the debugger has been disconnected. 3.6.16 Software Debug Notes and Errata • Trace buffer message count value on data aborts: LDR to non-PC that aborts gets counted in the exception message.
Page 157: Performance Monitoring
The hardware for the IXP45X/IXP46X network processors provides four 32-bit performance counters that allow four unique events to be monitored simultaneously. In addition, the IXP45X/IXP46X network processors implement a 32-bit clock counter that can be used in conjunction with the performance counters; its main purpose is to count the number of core clock cycles which is useful in measuring total execution time.
Page 158: Register Description
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor 3.7.2 Register Description Table 56. Register Legend Attribute Legend Attribute Legend Reserved Read Clear Preserved Read Only Read/Set Write Only Read/Write Not Accessible Normal Read...
Page 159: Performance Monitor Control Register
E and ID are 0, others unpredictable Bits Access Description Performance Monitor Identification (ID) - 31:24 Read / Write Ignored IXP45X/IXP46X network processors = 0x14 23:4 Read-unpredictable / Write-as-0 Reserved Clock Counter Divider (D) - Read / Write 0 = CCNT counts every processor clock cycle...
Page 160: Overflow Flag Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Table 60. Interrupt Enable Register (Sheet 2 of 2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 161: Event Select Register
® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 61. Overflow Flag Status Register (Sheet 2 of 2) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 162: Managing The Performance Monitor
B and BL instructions, in both Intel StrongARM and Thumb mode.) ® Branch incorrectly predicted. (Counts only B and BL instructions, in both Intel StrongARM and Thumb mode.) Instruction executed. Stall because the data cache buffers are full. This event will occur every cycle in which the condition is present.
Page 163: Instruction Cache Efficiency Mode
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 63. Performance Monitoring Events (Sheet 2 of 2) Event Number Event Definition (evtCountx) Data cache miss, not including Cache Operations (defined in “Register 7: Cache Functions”...
Page 164: Instruction Fetch Latency Mode
This statistic lets you know if the duration event cycles are due to many requests or are attributed to just a few requests. If the average is high, the IXP45X/IXP46X network processors may be starved of the bus external to the IXP45X/IXP46X network processors.
Page 165: Stall/Write-Back Statistics
When an instruction requires the result of a previous instruction and that result is not yet available, the IXP45X/IXP46X network processors stall in order to preserve the correct data dependencies. PMN0 counts the number of stall cycles due to data- dependencies.
Page 166: Multiple Performance Monitoring Run Statistics
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor PMN1 counts the number of data TLB table-walks, which occurs when there is a TLB miss. If the data TLB is disabled PMN1 will not increment.
Page 167: Programming Model
Intel StrongARM V5TE introduces a few more architecture features over Intel StrongARM V4, specifically the addition of tiny pages (1 Kbyte), a new instruction that counts the leading zeroes (CLZ) in a data value, enhanced Intel StrongARM-Thumb transfer instructions and a modification of the system control coprocessor, CP15.
Page 168: Intel Strongarm Architecture Implementation Options
StrongARM Architecture Implementation Options 3.8.2.1 Big-Endian versus Little-Endian The IXP45X/IXP46X network processors can operate in big or little endian mode. The B- bit of the Control Register, coprocessor 15, register 1, bit 7 (see Section 3.5.1.2) contained within the IXP45X/IXP46X network processors selects the endianess mode of the Intel XScale processor.
Page 169: Base Register Update
• Both LDRD and STRD instructions will generate an alignment exception when the address bits [2:0] = 0b100. The transfers of two Intel StrongARM register values to a coprocessor (MCRR) and the transfer of values from a coprocessor to two Intel StrongARM registers (MRRC) are only supported on the IXP45X/IXP46X network processors when directed to coprocessor 0 and are used to access the internal accumulator.
Page 170: Multiply With Internal Accumulate Format
Two new fields were created for this format, acc and opcode_3. The acc field specifies one of eight internal accumulators to operate on and opcode_3 defines the operation for this format. The Intel XScale processor defines a single 40-bit accumulator referred to as acc0; future implementations may define multiple internal accumulators. The Intel XScale processor uses opcode_3 to define six instructions, MIA, MIAPH, MIABB, MIABT, MIATB and MIATT.
Page 171: Mia{} Acc0, Rm, Rs
185. Specifying R15 for register Rs or Rm has unpredictable results. acc0 is defined to be 0b000 on Intel XScale processor. The MIA instruction operates similarly to MLA except that the 40-bit accumulator is used. MIA multiplies the signed value in register Rs (multiplier) by the signed value in register Rm (multiplicand) and then adds the result to the 40-bit accumulator (acc0).
Page 172: Miaxy{} Acc0, Rm, Rs
185. Specifying R15 for register Rs or Rm has unpredictable results. acc0 is defined to be 0b000 on Intel XScale processor. The MIAxy instruction performs one16-bit signed multiply and accumulates these to a single 40-bit accumulator. x refers to either the upper half or lower half of register Rm (multiplicand) and y refers to the upper or lower half of Rs (multiplier).
Page 173: Internal Accumulator Access Format
® The RdHi and RdLo fields allow up to 64 bits of data transfer between Intel StrongARM registers and an internal accumulator. The acc field specifies 1 of 8 internal accumulators to transfer data to/from.
Page 174: Mar{} Acc0, Rdlo, Rdhi
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Table 70. MAR{<cond>} acc0, RdLo, RdHi 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 175: New
3.8.3.2 New Page Attributes The Intel XScale processor extends the page attributes defined by the C and B bits in the page descriptors with an additional X bit. This bit allows four more attributes to be encoded when X=1. These new encodings include allocating data for the mini-data cache and write-allocate caching.
Page 176: Additions To Cp15 Functionality
Small page base address Tiny Page Base Address The TEX (Type Extension) field is present in several of the descriptor types. In the Intel XScale processor, only the LSB of this field is defined; this is called the X bit. The remaining bits are reserved for future use and should be programmed as zero (SBZ) on the IXP45X/IXP46X network processors.
Page 177: Event Architecture
3.8.3.4 Event Architecture 3.8.3.4.1 Exception Summary Table 75 shows all the exceptions that the Intel XScale processor may generate, and the attributes of each. Subsequent sections give details on each exception. Table 75. Exception Summary Exception Description Exception Type...
Page 178: Processors': Encoding Of Fault Status For Prefetch Aborts
3.8.3.4.4 Data Aborts Two types of data aborts exist in the Intel XScale processor: precise and imprecise. A precise data abort is defined as one where R14_ABORT always contains the PC (+8) of the instruction that caused the exception. An imprecise abort is one where R14_ABORT contains the PC (+4) of the next instruction to execute and not the address of the instruction that caused the abort.
Page 179 The Fault Address Register for all imprecise data aborts is undefined and R14_ABORT is ® the address of the next instruction to execute + 4, which is the same for both Intel StrongARM and Thumb mode. Although the Intel XScale processor guarantees the Base Restored Abort Model for precise aborts, it cannot do so in the case of imprecise aborts.
Page 180: Events From Preload Instructions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Example 18. Shielding Code from Potential Imprecise Aborts ;; Example of code that maintains architectural state through the ;; window where an imprecise fault might occur.
Page 181: Performance Considerations
Performance Considerations This section describes relevant performance considerations that compiler writers, application programmers, and system designers need to be aware of to efficiently use the IXP45X/IXP46X network processors. Performance numbers discussed here include interrupt latency, branch prediction, and instruction latencies. 3.9.1...
Page 182: Branch Prediction
A penalty of zero for correct prediction means that the IXP45X/IXP46X network processors can execute the next instruction in the program flow in the cycle following the branch.
Page 183 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors • Cycle Distance from A to B The cycle distance from cycle A to cycle B is (B-A) -- that is, the number of cycles from the start of cycle A to the start of cycle B. Example: the cycle distance from cycle 3 to cycle 4 is one cycle.
Page 184: Branch Instruction Timings
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor the code fragment, there is a result dependency between the UMLAL instruction and the SUB instruction. In Table 80, UMLAL starts to issue at cycle 0 and the SUB issues at cycle 5.
Page 185: Multiply Instruction Timings
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 83. Data Processing Instruction Timings (Sheet 2 of 2) <shifter operand> is a Shift/Rotate <shifter operand> is NOT a Shift/ by Register OR Rotate by Register <shifter operand>...
Page 186 ® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Table 84. Multiply Instruction Timings (Sheet 2 of 2) Rs Value S-Bit Minimum Minimum Result Minimum Resource Mnemonic (Early Valu Issue † Latency Latency (Throughput)
Page 187: Saturated Arithmetic Instructions
® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 85. Multiply Implicit Accumulate Instruction Timings Minimum Resource Rs Value (Early Minimum Issue Minimum Result Mnemonic Latency Termination) Latency Latency (Throughput) Rs[31:15] = 0x0000...
Page 188: Semaphore Instructions
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor Table 89. Load and Store Instruction Timings Mnemonic Minimum Issue Latency Minimum Result Latency LDRSH 3 for load data; 1 for writeback of base LDRT 3 for load data;...
Page 189: Miscellaneous Instruction Timing
This is due to the branch latency penalty. (See Table 79 on page 182.) ® • A Thumb BL instruction when H = 0 will have the same timing as an Intel StrongARM data processing instruction. ® The mapping of Thumb instructions to Intel...
Page 190: About This Section
• Certain instructions incur a few extra cycles of delay on the IXP45X/IXP46X ® network processors as compared to Intel StrongARM processors (LDM, STM). • Decode and register file lookups are spread out over two cycles in the IXP45X/ IXP46X network processors, instead of one cycle in predecessors. ® ® Intel...
Page 191: Risc Super-Pipeline
Sequential consistency of instruction execution relates to two aspects: first, to the order in which the instructions are completed; and second, to the order in which memory is accessed due to load and store instructions. The IXP45X/IXP46X network processors preserve a weak processor consistency because instructions may complete out of order, provided that no data dependencies exist.
Page 192: Instruction Flow Through The Pipeline
All load/store instructions are routed to the memory pipeline after the effective addresses have been calculated in X1. The Intel StrongARM V5TE bx (branch and exchange) instruction, which is used to branch between Intel StrongARM and thumb code, causes the entire pipeline to be flushed (The bx instruction is not dynamically predicted by the BTB).
Page 193: Main Execution Pipeline
The progress of an instruction can stall anywhere in the pipeline. Several pipe stages may stall for various reasons. It is important to understand when and how hazards occur in the IXP45X/IXP46X network processors’ pipeline. Performance degradation can be significant if care is not taken to minimize pipeline stalls.
Page 194: Memory Pipeline
RFU will stop stalling the pipe. The Intel StrongARM architecture specifies that one of the operands for data processing instructions as the shifter operand, where a 32-bit shift can be performed before it is used as an input to the ALU.
Page 195: Multiply/Multiply Accumulate (Mac) Pipeline
3.10.3 Basic Optimizations This section outlines optimizations specific to Intel StrongARM architecture. These optimizations have been modified to suit the IXP45X/IXP46X network processors where needed. 3.10.3.1 Conditional Instructions The IXP45X/IXP46X network processors’ architecture provides the ability to execute instructions conditionally.
Page 196 ® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor if (a + b) Code generated for the if condition without using an add instruction to set condition codes is: ;Assume r0 contains the value a, and r1 contains the value b...
Page 197 In the case of the IXP45X/IXP46X network processors, a branch misprediction incurs a penalty of four cycles. If the branch is incorrectly predicted 50 percent of the time, and if we assume that both the if-part and the else-part are equally likely to be taken, on an average the code above takes 5.5 cycles to execute.
Page 198 ® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor if (cond) if_stmt else else_stmt Assume that we have the following data: • N1 ....Number of cycles to execute the if_stmt assuming the use of branch instructions •...
Page 199: Bit Field Manipulation
This approach also reduces the utilization of branch prediction resources. 3.10.3.2 Bit Field Manipulation The shift and logical operations of the IXP45X/IXP46X network processors provide a useful way of manipulating bit fields. Bit field operations can be optimized as follows: ® ®...
Page 200: Optimizing The Use Of Immediate Values
3.10.3.3 Optimizing the Use of Immediate Values The MOV or MVN instruction of the IXP45X/IXP46X network processors should be used when loading an immediate (constant) value into a register. Please refer to the ARM* Architecture Reference Manual for the set of immediate values that can be used in a MOV or MVN instruction.
Page 201: Effective Use Of Addressing Modes
3.10.3.5 Effective Use of Addressing Modes The IXP45X/IXP46X network processors provide a variety of addressing modes that make indexing an array of objects highly efficient. For a detailed description of these addressing modes please refer to the ARM* Architecture Reference Manual. The...
Page 202 For the IXP45X/IXP46X network processors, care must be taken to optimize code to have a maximum cache hit when accesses have been requested to the Expansion Bus Interface or the PCI Bus Controller.
Page 203: Data And Mini Cache
This distribution unevenness can lead to excessive thrashing of the Data and Mini Caches. 3.10.4.2 Data and Mini Cache The IXP45X/IXP46X network processors allow the user to define memory regions whose cache policies can be set by the user (see “Cacheability” on page 88). Supported policies and configurations are: •...
Page 204 Application performance can be improved by converting a part of the cache into on chip RAM and allocating frequently allocated variables to it. Due to the round-robin replacement policy of the IXP45X/IXP46X network processors, all data will eventually be evicted. Therefore to prevent critical or frequently used data from being evicted it should be allocated to on-chip RAM.
Page 205: Data Alignment
® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors • The stack space of a frequently occurring interrupt, the stack is used only during the duration of the interrupt, which is usually very small. • Video buffers, these are usual large and can occupy the whole cache.
Page 206: Cache Considerations
3.10.4.2.7 Literal Pools The IXP45X/IXP46X network processors do not have a single instruction that can move all literals (a constant or address) to a register. One technique to load registers with literals in the IXP45X/IXP46X network processors is by loading the literal from a memory location that has been initialized with the constant or address.
Page 207: Prefetch Considerations
Prefetch also applies to data writing when the memory type is enabled as write- allocate. The prefetch load instruction of the IXP45X/IXP46X network processors is a true prefetch instruction because the load destination is the data or mini-data cache and not a register.
Page 208 Similarly rearranging sections of data structures so that sections often written fit in the same half cache line, 16 bytes for the IXP45X/IXP46X network processors, can reduce cache eviction write-backs. On a global scale, techniques such as array merging can enhance the spatial locality of the data.
Page 209 ® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors struct { int a; int b; } c_arrays; int ix; for (i=0; i<NMAX]; i++) ix = c[i].b; if (c[i].a != 0) ix = c[i].a; do_other_calculations;...
Page 210 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor The variable A[i][k] is completely reused. However, accessing C[j][k] in the j and k loops can displace A[i][j] from the cache. Using blocking the code becomes: for(i=0;...
Page 211 ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Recursive data structure traversal is another construct where prefetching can be applied. This is similar to linked list traversal. Consider the following pre-order traversal of a binary tree:...
Page 212: Instruction Scheduling
3.10.5.1 Scheduling Loads On the IXP45X/IXP46X network processors, an LDR instruction has a result latency of three cycles assuming the data being loaded is in the data cache. If the instruction after the LDR needs to use the result of the load, then it would stall for 2 cycles. If possible, the instructions surrounding the LDR instruction should be rearranged.
Page 213 ® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors to avoid this stall. Consider the following example: r1, r2, r3 r0, [r5] r6, r0, r1 r8, r2, r3 r9, r2, r3 In the code shown above, the ADD instruction following the LDR would stall for two cycles because it uses the result of the load.
Page 214 #0xf ; The value in register r6 is not used after this The IXP45X/IXP46X network processors have four fill-buffers that are used to fetch data from external memory when a data-cache miss occurs. The IXP45X/IXP46X network processors stall when all fill buffers are in use. This happens when more than 4 ®...
Page 215 3.10.5.1.1 Scheduling Load and Store Double (LDRD/STRD) The IXP45X/IXP46X network processors introduce two new double word instructions: LDRD and STRD. LDRD loads 64 bits of data from an effective address into two consecutive registers, conversely, STRD stores 64 bits from two consecutive registers to an effective address.
Page 216: Scheduling Data Processing Instructions
3.10.5.2 Scheduling Data Processing Instructions Most data processing instructions for the IXP45X/IXP46X network processors have a result latency of one cycle. This means that the current instruction is able to use the result from the previous data processing instruction. However, the result latency is two cycles if the current instruction needs to use the result of the previous data processing instruction for a shift by immediate.
Page 217: Scheduling Multiply Instructions
® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors All data processing instructions incur a two cycle issue penalty and a two-cycle result penalty when the shifter operand is a shift/rotate by a register or shifter operand is RRX.
Page 218: Scheduling Swp And Swpb Instructions
® ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale Processor 3.10.5.4 Scheduling SWP and SWPB Instructions The SWP and SWPB instructions have a five-cycle issue latency. As a result of this latency, the instruction following the SWP/SWPB instruction would stall for 4 cycles.
Page 219: Scheduling The Mia And Miaph Instructions
® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors The MAR (MCRR) instruction has an issue latency, a result latency, and a resource latency of two cycles. Due to the two-cycle issue latency, the pipeline would always stall for one cycle following a MAR instruction.
Page 220: Scheduling Cp15 Coprocessor Instructions
For applications such as cell phone software it is necessary to optimize the code for improved performance while minimizing code size. Optimizing for smaller code size will, in general, lower the performance of your application. This section contains techniques for optimizing for code size using the instruction set for the IXP45X/IXP46X network processors. 3.10.7.1...
Page 221 ® ® ® Intel XScale Processor—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3.10.7.1.2 Use of Conditional Instructions Using conditional instructions to expand if-then-else statements as described in “Conditional Instructions” on page 195 will result in increasing the size of the generated code.
Page 222: Network Processor Engines (Npe)
MII (MAC), CRC checking/generation, AAL2, DES, AES, SHA, MD5, etc. Note: Certain NPEs are not available, depending on which variant of the IXP45X/IXP46X network processors is used. Table 97 shows which network-processor models have which NPEs enabled.
Page 223 Intel XScale processor. Note: All the described NPE functions require Intel-supplied software executing on the NPEs. ® For further information, see the Intel IXP400 Software Programmer’s Guide. For information on the availability of the NPE software and its enabling functions, contact your local sales representative.
Page 224: Internal Buses
NPEs on the North AHB and the DDRI SDRAM. The South AHB is a 133-MHz, 32-bit bus that can be mastered by the Intel XScale processor, PCI Controller, Expansion Bus Controller, USB Host 2.0, and the AHB/AHB Bridge.
Page 225: Internal Bus Arbiters
IXP46X Product Line of Network Processors Internal Bus Arbiters The IXP45X/IXP46X network processors contain two internal bus arbiters, one arbiter for North AHB transactions and one arbiter for South AHB transactions. The arbiters are used to ensure that at any particular time only one AHB master has access to a given AHB.
Page 226: Memory Map
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Internal Buses Table 98. Bus Arbitration Example: Three Requesting Masters Initial Requesting Masters Winning Bus Initiator Memory Map Table 99 shows the memory map of peripherals connected to the AHB.
Page 227 ® ® Internal Buses—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 99. Memory Map (Sheet 2 of 2) Start Address End Address Size NPE-C (IXP400 software Definition) – Not User C800_8000 C800_8FFF 1 KB Programmable C800_9000 C800_9FFF...
Page 228 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Internal Buses ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 229: Ethernet Macs
Table 97, “Processors: Network Processor Functions” on page 222. The IXP45X/IXP46X network processors contain three NPEs. All of the NPEs may be used to process Ethernet traffic utilizing the xMII (MII/SMII) interfaces. Each NPE core used for Ethernet traffic connects to a Transmit FIFO and Receive FIFO through the NPE Coprocessor interface.
Page 230: Ethernet Coprocessor
6.1.1 Ethernet Coprocessor APB Interface The APB interface is used to allow the Intel XScale processor to communicate directly to configuration and control registers utilized by the Media Access Controller. The Ethernet coprocessor’s APB interface will be used to configure the Ethernet MAC, monitor Ethernet status, and configure the physical devices connected via the MII interfaces.
Page 231: Ethernet Coprocessor Mdio Interface
(MDIOCMD). The MDIO Command Register is broken into four 8-bit registers that make up a full 32-bit command word. If data is to be sent to the PHY over the MDIO interface, the Intel XScale processor will write a value to each of the four command words in sequential order: •...
Page 232: Mdio Write
Figure 31 shows an example of the data being read from the physical interface (PHY) by the xMII Management Master (IXP45X/IXP46X network processors) using the MDIO interface. These registers should be manipulated using Intel-supplied APIs. Figure 30. MDIO Write...
Page 233: Transmitting Ethernet Frames With Mii Interfaces
When the preparation is complete, the Intel XScale processor uses the Intel-supplied API calls to inform the Ethernet NPE that a packet is ready to be transmitted. The Ethernet NPE fetches the packet from the memory attached to the IXP45X/IXP46X network processors and forwards the data over the NPE coprocessor interface to the 256-byte Transmit FIFO contained in the Ethernet coprocessor.
Page 234 • Setting this bit to logic 0 will cause a transmitted frame to be sent without a Frame Check Sequence attached. Transmit Control Register 1 can be accessed directly, but Intel recommends that the Transmit Control Register 1 values be manipulated through Intel-supplied APIs. Failure to use the Intel-supplied APIs will result in unpredictable results.
Page 235 Transmit Two Part Deferral Parameters 2 Register. When the xMII interface of the IXP45X/IXP46X network processors is configured in full- duplex mode of operation, the two-part transmit deferral parameters and the back-off times will not be utilized for data transmission.
Page 236: Receiving Ethernet Frames With Mii Interfaces
Intel recommends that these register values be manipulated through Intel- supplied APIs. Failure to use the Intel-supplied APIs will result in unpredictable results. In order to operate the interface in SMII mode, the Ethernet registers will be configured as if they are in MII mode of operation.
Page 237 ® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors Setting bit 5 of Receive Control Register 1 (RXCTRL1) to logic 1 enables filtering for uni- cast frames that are received. When Uni-Cast frames are detected, the destination address of the received frame must match exactly the value contained in the Uni-Cast Address Register (UNIADDR).
Page 238: General Ethernet Coprocessor Configuration
Bit 0 of Receive Control Register 2 (RXCTRL2) enables deferral checking on the receive side. The IXP45X/IXP46X network processors do not use the receive side deferral checking feature.
Page 239: Register Descriptions Ethernet Macs
Setting bit 4 of the Core Control (CORE_CONTROL) Register to logic 1 enables the IXP45X/IXP46X network processors to drive the MDC clock. Setting bit 4 of the Core Control (CORE_CONTROL) Register to logic 0 enables an external source to drive the MDC clock.
Page 240: Ethernet Mac 0 On Npe B
Write ‘1’ to set All of the Ethernet internal configuration and control registers are directly readable and writable by the Intel XScale processor via APB bus. All registers for all MII interfaces will match the detailed register descriptions contained in this chapter.
Page 241: Ethernet Mac 1 On Npe B
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 101. Ethernet MAC 0 on NPE B (Sheet 2 of 2) Address Description 0xC800 90B4 Address Mask 6 0xC800 90C0 Address 1 0xC800 90C4 Address 2...
Page 242 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs Table 102. Ethernet MAC 1 on NPE B (Sheet 2 of 2) Address Description 0xC800 D088 MDIO Command 3 0xC800 D08C MDIO Command 4 0xC800 D090 MDIO Status 1...
Page 243: Ethernet Mac 2 On Npe B
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.3 Ethernet MAC 2 on NPE B Table 103. Ethernet MAC 2 on NPE B (Sheet 1 of 2) Address Description 0xC800 E000 Transmit Control 1 0xC800 E004...
Page 244: Ethernet Mac 2 On Npe B
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs Table 103. Ethernet MAC 2 on NPE B (Sheet 2 of 2) Address Description 0xC800 E0CC Address 4 0xC800 E0D0 Address 5 0xC800 E0D4 Address 6 0xC800 E0E0...
Page 245 ® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 104. Ethernet MAC 2 on NPE B (Sheet 2 of 2) Address Description 0xC800 F08C MDIO Command 4 0xC800 F090 MDIO Status 1 0xC800 F094 MDIO Status 2...
Page 246: Ethernet Mac On Npe A
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.5 Ethernet MAC on NPE A Table 105. Ethernet MAC on NPE A (Sheet 1 of 2) Address Description 0xC800 C000 Transmit Control 1 0xC800 C004 Transmit Control 2...
Page 247: Ethernet Mac On Npe C
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 105. Ethernet MAC on NPE A (Sheet 2 of 2) Address Description 0xC800 C0CC Address 4 0xC800 C0D0 Address 5 0xC800 C0D4 Address 6 0xC800 C0E0...
Page 248 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs Table 106. Ethernet MAC on NPE C (Sheet 2 of 2) Address Description † 0xC800 A088 MDIO Command 3 † 0xC800 A08C MDIO Command 4 † 0xC800 A090 MDIO Status 1 †...
Page 249: Transmit Control 1
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.7 Transmit Control 1 txctrl1 Register Name: 0xC8009000 0x00000000 Hex Offset Address: Reset Hex Value: Register Transmit Control Register Description: Access: Read/Write. (Reserved) Register txctrl1 Bits Name...
Page 250: Receive Control 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.9 Receive Control 1 rxctrl1 Register Name: 0xC8009010 0x00000000 Hex Offset Address: Reset Hex Value: Register Receive Control Register Description: Access: Read/Write. (Reserved) Register rxcrtl1 Bits Name...
Page 251: Receive Control 2
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.10 Receive Control 2 rxctrl2 Register Name: 0xC8009014 0x00000000 Hex Offset Address: Reset Hex Value: Register Receive Control Register Description: Access: Read/Write. (Reserved) rxctrl2 Register Bits Name...
Page 252: Threshold For Partially Full
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs Register threshpe Bits Name Description 31:8 (Reserved) Marks the partial empty thresholds of the Transmit FIFO and Receive FIFO. When the number of entries in the Transmit FIFO is less than or equal to the Partial Empty contents of this register, tx_fifo_p_empty is asserted.
Page 253: Transmit Deferral Parameter
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.15 Transmit Deferral Parameter txdefpars Register Name: 0xC8009050 0x00000000 Hex Offset Address: Reset Hex Value: Register Transmit/Receive Deferral Parameters Description: Access: Read/Write. (Reserved) Transmit Deferral Register txdefpars...
Page 254: Transmit Two Part Deferral Parameters 2
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs Register txdefpars Bits Name Description 31:8 (Reserved) Number of transmit clock cycles (tx_clk) in the first deferral period minus three, First deferral when two-part deferral is used for transmission (Transmit Control 1[5] = 1) and period half-duplex mode.
Page 255: Mdio Command 1
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors • MDIO Command[23:16] — MDIO Command 3 • MDIO Command[15:8] — MDIO Command 2 • MDIO Command[7:0] — MDIO Command 1 The detailed bit descriptions follow the four commands’ bit maps.
Page 256: Mdio Command 4
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.24 MDIO Command 4 mdiocm4 Register Name: 0x C800908C 0x00000000 Hex Offset Address: Reset Hex Value: Register MDIO Command Register Description: Access: Read/Write. 31 30 (Reserved) MDIO_COMMAND[31:24]...
Page 257: Mdio Status 2
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.27 MDIO Status 2 mdiosts2 Register Name: 0x C8009094 0x00000000 Hex Offset Address: Reset Hex Value: Register MDIO Status Register Description: Access: Read Only. (Reserved) MDIO_STATUS[15:8] 6.2.28...
Page 258: Address Mask 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs • Address Mask[23:16] — Address Mask 4 • Address Mask[15:8] — Address Mask 5 • Address Mask[7:0] — Address Mask 6 Example: Address Mask is 00-A0-24-D1-7F-02 • Address Mask 1 = 0x00 •...
Page 259: Address Mask 3
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.33 Address Mask 3 addrmask3 Register Name: 0x C80090A8 0x00000000 Hex Offset Address: Reset Hex Value: Address Mask Register #1. Third register of six that makes up the Address Mask. Address Mask is used with Address for multicast address filtering.
Page 260: Address Mask 6
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.36 Address Mask 6 addrmask6 Register Name: 0x C80090B4 0x00000000 Hex Offset Address: Reset Hex Value: Address Mask Register #1. Sixth register of six that makes up the Address Mask. Address Mask is used with Address for multicast address filtering.
Page 261: Address 1
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.38 Address 1 addr1 Register Name: 0x C80090C0 0x00000000 Hex Offset Address: Reset Hex Value: Address Register #1. First register of six that makes up the Address. Address Mask is used with Address for multicast address filtering.
Page 262: Address 4
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.41 Address 4 addr4 Register Name: 0x C80090CC 0x00000000 Hex Offset Address: Reset Hex Value: Address Register #1. Forth register of six that makes up the Address. Address Mask is used with Address for multicast address filtering.
Page 263: Threshold For Internal Clock
Example: 25 MHz PHY clock, 133 MHz application clock — Sets this register to 1. Any application, clock frequency greater than the tx_clk or rx_clk frequency will have a clock ratio of 1. Always set to 1 for the IXP45X/IXP46X network processors.
Page 264: Unicast Address 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Ethernet MACs 6.2.46 Unicast Address 1 uniaddr1 Register Name: 0x C80090F0 0x00000000 Hex Offset Address: Reset Hex Value: Unicast Address Register #1. First register of six that makes up the Unicast Address.
Page 265: Unicast Address 5
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors 6.2.50 Unicast Address 5 uniaddr5 Register Name: 0x C8009100 0x00000000 Hex Offset Address: Reset Hex Value: Unicast Address Register #1. Fifth register of six that makes up the Unicast Address.
Page 266 (Reserved) 1 = Configures the MDC as an output clock. Mdc_en Set to 1 for the IXP45X/IXP46X network processors MAC0 on NPE B. This bit is set as Reserved for MACs on NPE A and NPE C Send_jam 1 = Causes a jam sequence to be sent if reception of a packet begins.
Page 267: August 2006 Developer's Manual
® ® Ethernet MACs—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual Order Number: 306262-004US...
Page 268: Utopia Level 2
Processors. The features accessible by the user are described in the Intel IXP400 Software Programmer’s Guide and may be a subset of the features described in this chapter. Note: Not all of the IXP45X/IXP46X network processors have this functionality. For details, ® ® see Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s...
Page 269: Utopia Transmit Module
The ATM Adaptation Layers (AAL) implemented by the Network Processor Engine may have some further limitations on the number of physical interfaces supported. For more ® details on the number of physical interfaces supported, see the Intel IXP400 Software Programmer’s Guide.
Page 270 The physical interface is configured to the address signals that match the values contained on the UTP_OP_ADDR signals and responds to the UTOPIA Level 2 interface on the IXP45X/ IXP46X network processors by driving the UTP_OP_FCI (a.k.a TX_FULL_N/TX_CLAV) signal to inform the UTOPIA Level 2 Interface that the physical interface is ready to receive a cell.
Page 271: Utopia Level 2 Mphy Transmit Polling
• Notice on clock cycles 19 and 20 that Physical Interface G is selected as the next Physical Interface that the IXP45X/IXP46X network processors will transmit data Figure 33. UTOPIA Level 2 MPHY Transmit Polling...
Page 272: Utopia Receive Module
1s. In octet-level single-PHY (SPHY) mode, the physical interface indicates to the UTOPIA Level 2 Interface on the IXP45X/IXP46X network processors that the physical interface can accept data by de-asserting UTP_OP_FCI (also known as TX_FULL_N/TX_CLAV) signal. The UTOPIA Level 2 Interface subsequently transmits data to the PHY at the same time, asserting UTP_OP_FCO (also known as TX_ENB_N).
Page 273 The physical interface that is prepared to send a cell — and configured to the address signals that match the values contained on the UTP_IP_ADDR signals — responds to the UTOPIA Level 2 Interface on the IXP45X/IXP46X network processors by driving the UTP_IP_FCI (also known as RX_EMPTY_N/RX_CLAV) signal, to inform the UTOPIA Level 2 Interface that the physical interface is ready to send a cell.
Page 274: Utopia Level 2 Mphy Receive Polling
G has a full cell ready for the IXP45X/IXP46X network processors. The UTP_IP_FCI signal flags that a full cell is ready to be sent by Physical Interface G to the IXP45X/ IXP46X network processors, asserting the UTP_IP_FCI to logic 1 one clock after Physical Interface G has been polled.
Page 275: Utopia Level 2 Coprocessor / Npe Coprocessor: Bus Interface
The multiple-PHY (MPHY) address translation is used by the UTOPIA Level 2 Interface, on the IXP45X/IXP46X network processors, to poll physical addresses that are not contiguous or do not start at 0.
Page 276: Utopia Level 2 Clocks
1, 3, 5, 7, 0, 2, 4, 6. UTOPIA Level 2 Clocks The UTOPIA Level 2 interface on the IXP45X/IXP46X network processors characterizes the interface for clock speeds of 25 MHz and 33 MHz. The UTOPIA Level 2 interface requires both transmit and receive clock inputs to be supplied from an external source.
Page 277 ® ® UTOPIA Level 2—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual Reference Number: 306262-004US...
Page 278: Usb 1.1 Device Controller
A working knowledge of the USB standard is vital to effective use of this chapter. The ® ® Universal Serial Bus Device Controller (UDC) of the Intel IXP45X and Intel IXP46X Product Line of Network Processors is USB-compliant and supports all standard device requests issued by the host.
Page 279: Device Configuration
The UDC uses a dual-port memory to support FIFO operations. Each Bulk and Isochronous Endpoint FIFO structure is double-buffered to enable the endpoint to process one packet as it assembles another. The Intel XScale processor can fill and empty the FIFOs. An interrupt is generated when a packet has been received.
Page 280: Usb Operation
USB Operation After an Intel XScale processor reset — or when the USB host issues a USB reset — the UDC configures all endpoints and is forced to use the USB default address, 0. After the UDC configures the endpoints, the USB host assigns the UDC a unique address.
Page 281: Bit Encoding
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors By decoding the polarity of the UDC+ and UDC- pins and using differential data, four distinct states are represented. Two of the four states are used to represent data. A 1 indicates that UDC+ is high and UDC- is low.
Page 282: Field Formats
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller Each time a 0 occurs, the receiver logic synchronizes the baud clock to the incoming data (thus producing the clock). To ensure the receiver is periodically synchronized, any time six consecutive 1s are detected in the serial bit stream, a 0 is automatically inserted by the transmitter.
Page 283: Packet Formats
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The host is then responsible for assigning a unique address to each device on the bus. Addresses are assigned in the enumeration process, one device at a time. After the host assigns the an address to the UDC, the UDC only responds to transactions directed to that address.
Page 284: Token Packet Type
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller • Token • Data • Handshake • Special A PRE (Preamble) PID precedes a low-speed (1.5 Mbps) USB transmission. The UDC supports high-speed (12 Mbps) USB transfers only. PRE packets that signify low-speed devices and the low-speed data transfer that follows such PRE packets are ignored.
Page 285: Handshake Packet Type
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 112. Data Packet Format 8 Bits 8 Bits 0 - 1,023 Bytes 16 Bits Sync Data CRC16 8.3.4.4 Handshake Packet Type Handshake packets consist of a Sync and a PID. Handshake packets do not contain a CRC because the PID contains its own check field.
Page 286: Isochronous Transaction Type
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller Table 114. Bulk Transaction Formats † † Action Token Packet Data Packet Handshake Packet Host successfully received data from UDC DATA0/DATA1 UDC temporarily unable to transmit data...
Page 287: Interrupt Transaction Type
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors To assemble control transfers, the host sends a control transaction to tell the UDC what type of control transfer is taking place (control read or control write), followed by one or more data transactions.
Page 288: Udc Configuration
Enables a specific feature such as device remote wake-up or endpoint stalls. CLEAR_FEATURE Clears or disables a specific feature. Configures the UDC for operation. Used after a reset of the Intel XScale SET_CONFIGURATION processor or after a reset has been signalled via the USB.
Page 289: Udc Hardware Connections
64 bytes or less, and isochronous endpoints with a maximum packet size of 256 bytes or less. To make the IXP45X/IXP46X network processors more adaptable, the UDC supports a total of four configurations. Each of these configurations are identical in the UDC, software can make three distinct configurations, each with two interfaces.
Page 290: Register Legend
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller A control register enables the UDC and masks the interrupt sources in the UDC. A status register indicates the state of the interrupt sources. Each of the 16 endpoints (control, OUT, and IN) have a control or status register.
Page 291: Udc Control Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 120. USB-Device Register Descriptions (Sheet 2 of 2) Address Name Description 0 x C800 B068 UBC2 UDC Byte Count Register 2 0 x C800 B06C...
Page 292: Udc Active
USB host controller issues an UDC reset. Programming REM does not affect the state of RSTIR. The UDE bit is cleared to 0, which disables the UDC following a Intel XScale processor reset. Writes to reserved bits are ignored and reads return zeros.
Page 293: Udc Endpoint 0 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCR Register Name: 0XC800B000 0x000000A0 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Control Register Description: Access: Read/Write and Read-Only Bits...
Page 294: Out Packet Ready (Opr)
8.5.2.2 IN Packet Ready (IPR) The IN packet ready bit is set by the Intel XScale processor if less than max_packet bytes (16) have been written to the endpoint 0 FIFO to be transmitted. The Intel XScale processor must not set this bit if a max_packet is to be transmitted. The UDC clears this bit when the packet has been successfully transmitted, the UDCCS0[FTF] bit has been set, or a control OUT is received.
Page 295: Force Stall (Fst)
8.5.2.6 Force Stall (FST) The force stall bit can be set by the Intel XScale processor to force the UDC to issue a STALL handshake. The UDC issues a STALL handshake for the current setup control transfer and the bit is cleared by the UDC because endpoint 0 cannot remain in a stalled condition.
Page 296: Udc Endpoint 1 Control/Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UDCCS0 Register (Sheet 2 of 2) Bits Name Description Flush Tx FIFO (always read 0/write 1 to set) 1 = Flush the contents of Tx FIFO.
Page 297: Sent Stall (Sst)
8.5.3.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 298: Udc Endpoint 2 Control/Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UDCCS1 Register Bits Name Description 31:8 (Reserved) Transmit short packet (read/write 1 to set). 1 = Short packet ready for transmission. (Reserved). Always reads 0.
Page 299: Sent Stall (Sst)
8.5.4.6 Force Stall (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 300: Udc Endpoint 3 Control/Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UDCCS2 Register Name: 0 x C800 B018 0 x 00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Endpoint 2 Control and Status Register...
Page 301: Transmit Packet Complete (Tpc)
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.5.2 Transmit Packet Complete (TPC) The UDC sets transmit packet complete bit when an entire packet is sent to the host. When this bit is set, the IR3 bit in the appropriate UDC status/interrupt register is set if transmit interrupts are enabled.
Page 302: Udc Endpoint 4 Control/Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UDCCS3 Register Name: 0 x C800 B01C 0 x 00000001 Hex Offset Address: Reset Hex Value: Register Description: Universal Serial Bus Device Controller Endpoint 3 Control and Status...
Page 303: Receive Packet Complete (Rpc)
This bit is updated by the UDC after the last byte is read from the active buffer and reflects the status of the new active buffer. If UDCCS4[RSP] is a 1 and UDCCS4[RNE] is a 0, it indicates a zero-length packet. If a zero-length packet is present, the Intel XScale processor must not read the data register.
Page 304: Udc Endpoint 5 Control/Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UDCCS4 Register Name: 0x C800B020 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Endpoint 4 Control and Status Register Description:...
Page 305: Flush Tx Fifo (Ftf)
8.5.7.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 306: Bit 6 Reserved
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller 8.5.7.7 Bit 6 Reserved Bit 6 is reserved for future use. 8.5.7.8 Transmit Short Packet (TSP) Software uses the transmit short to indicate that the last byte of a data transfer has been sent to the FIFO.
Page 307: Udc Endpoint 6 Control/Status Register
UDCCS6[SST] bit is set. To allow the software to continue to send the STALL condition on the USB bus, the UDCCS6[FST] bit must be set again. The Intel XScale processor writes a 1 to the sent stall bit to clear it.
Page 308 8.5.8.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 309: Udc Endpoint 7 Control/Status Register
STALL on the USB bus. This bit is not set if the UDC detects a protocol violation from the host PC when a STALL handshake is returned automatically. In either event, the Intel XScale processor does not intervene and the UDC clears the STALL status when the host sends a CLEAR_FEATURE command.
Page 310 8.5.9.6 Force Stall (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 311: Udc Endpoint 8 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS7 Register Bits Name Description 31:8 Reserved for future use. Receive short packet (read only). 1 = Short packet received and ready for reading. Receive FIFO not empty (read-only).
Page 312 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller 8.5.10.3 Flush Tx FIFO (FTF) The Flush Tx FIFO bit triggers a reset for the endpoint’s transmit FIFO. The Flush Tx FIFO bit is set when software writes a 1 to it or when the host performs a SET_CONFIGURATION or SET_INTERFACE.
Page 313: Udc Endpoint 9 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS8 Register Bits Name Description 31:8 Reserved for future use. Transmit short packet (read/write 1 to set). 1 = Short packet ready for transmission. (Reserved). Always reads 0.
Page 314 If UDCCS9[RSP] is a one and UDCCS9[RNE] is a 0, it indicates a zero-length packet. If a zero-length packet is present, the Intel XScale processor must not read the data register. UDCCS9[RSP] clears when the next OUT packet is received.
Page 315: Udc Endpoint 10 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS9 Register (Sheet 2 of 2) Bits Name Description (Reserved) Receive overflow (read/write 1 to clear). 1 = Isochronous data packets are being dropped from the host because the receiver is full.
Page 316 8.5.12.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 317: Udc Endpoint 11 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS10 Register Bits Name Description 31:8 Reserved for future use. Transmit short packet (read/write 1 to set). 1 = Short packet ready for transmission. (Reserved). Always reads 0.
Page 318 8.5.13.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 319: Udc Endpoint 12 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS11 Register Name: 0 x C800B03C 0 x 00000001 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Endpoint 11 Control and Status Register...
Page 320: Sent Stall (Sst)
8.5.14.6 Force Stall (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 321: Receive Short Packet (Rsp)
If UDCCS12[RSP] is a 1 and UDCCS12[RNE] is a 0, it indicates a zero-length packet. If a zero-length packet is present, the Intel XScale processor must not read the data register. UDCCS12[RSP] is cleared when the next OUT packet is received.
Page 322: Transmit Fifo Service (Tfs)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller 8.5.15.1 Transmit FIFO Service (TFS) The transmit FIFO service bit is be set if one or fewer data packets remain in the transmit FIFO. UDCCS13[TFS] is cleared when two complete data packets are in the FIFO.
Page 323: Udc Endpoint 14 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS13 Register Name: 0 x C800 B044 0 x 00000001 Hex Offset Address: Reset Hex Value: Register Description: Universal Serial Bus Device Controller Endpoint 13 Control and Status...
Page 324: Receive Packet Complete (Rpc)
If UDCCS14[RSP] is a 1 and UDCCS14[RNE] is a 0, it indicates a zero-length packet. If a zero-length packet is present, the Intel XScale processor must not read the data register. UDCCS14[RSP] clears when the next OUT packet is received.
Page 325: Udc Endpoint 15 Control/Status Register
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UDCCS14 Register Name: 0x C800B048 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Endpoint 14 Control and Status Register Description:...
Page 326: Transmit Packet Complete (Tpc)
8.5.17.6 Force STALL (FST) The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL handshake to all IN tokens. STALL handshakes continue to be sent until the Intel XScale processor clears this bit by sending a Clear Feature command.
Page 327: Bit 6 Reserved
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.17.7 Bit 6 Reserved Bit 6 is reserved for future use. 8.5.17.8 Transmit Short Packet (TSP) Software uses the transmit short to indicate that the last byte of a data transfer has been sent to the FIFO.
Page 328: Udc Interrupt Control Register 0
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller 8.5.18 UDC Interrupt Control Register 0 (UICR0) The UICR0 contains eight control bits to enable/disable interrupt service requests from data endpoints 0 - 7. All of the UICR0 bits are reset to a 1 so interrupts are not generated on initial system reset.
Page 329: Udc Interrupt Control Register 1
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UICR0 Register (Sheet 2 of 2) Bits Name Description Interrupt Mask for Endpoint 2. 0 = Receive interrupt enabled. 1 = Receive interrupt disabled. Interrupt Mask for Endpoint 1.
Page 330: Udc Status/Interrupt Register 0
To clear status bits, the Intel XScale processor must write a 1 to the position to be cleared. The interrupt request for the UDC remains active as long as the value of the USIRx is non-zero.
Page 331: Endpoint 1 Interrupt Request (Ir1)
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.20.2 Endpoint 1 Interrupt Request (IR1) The interrupt request bit is set if the IM1 bit in the UDC interrupt control register is cleared and the IN packet complete (TPC) in UDC endpoint 1 control/status register is set.
Page 332: Udc Status/Interrupt Register 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller USIR0 Register Name: 0 x C800B058 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Interrupt Status Register 0 Description: Access: Read/Write and Read-Only...
Page 333: Endpoint 10 Interrupt Request (Ir10)
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The IR9 bit is cleared by writing a 1 to it. 8.5.21.3 Endpoint 10 Interrupt Request (IR10) The interrupt request bit is set if the IM10 bit in the UDC Interrupt Control Register is cleared and the IN packet complete (TPC) or in UDC endpoint 10 control/status register is set.
Page 334: Udc Frame Number High Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller USIR1 Register Name: 0 x C800B05C 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Controller Interrupt Status Register 1 Description: Access: Read/Write and Read-Only...
Page 335: August
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.22.2 Isochronous Packet Error Endpoint 4 (IPE4) The isochronous packet error for Endpoint 4 is set if Endpoint 4 is loaded with a data packet that is corrupted. This status bit is used in the interrupt generation of Endpoint To maintain synchronization, the software must monitor this bit when it services an SOF interrupt and reads the frame number.
Page 336: Udc Frame Number Low Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UFNHR Register Name: 0 x C800B060 0x00000040 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Frame Number High Register Description: Access: Read-Only...
Page 337: Udc Byte Count Register 2
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UFNLR Register Name: 0 x C800B064 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Frame Number Low Register Description: Access: Read-Only...
Page 338: Udc Byte Count Register 4
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UBCR2 Register Bits Name Description 31:8 (Reserved) Byte Count (read-only). Number of bytes in the FIFO is Byte Count plus 1 (BC+1) 8.5.25 UDC Byte Count Register 4...
Page 339: Endpoint 7 Byte Count (Bc[7:0])
® ® USB 1.1 Device Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 8.5.26.1 Endpoint 7 Byte Count (BC[7:0]) The byte count is updated after each byte is read. When software receives an interrupt that indicates the endpoint has data, it can read the byte count register to determine the number of bytes that remain to be read.
Page 340: Udc Byte Count Register 12
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device Controller UBCR9 Register Name: 0 x C800B074 0x00000000 Hex Offset Address: Reset Hex Value: Register Universal Serial Bus Device Endpoint 9 Byte Count Description: Access: Read-Only...
Page 341: Udc Byte Count Register 14
Endpoint 0 Register to access the data. When the UDC sends data to the host, the Intel XScale processor writes the data to be sent in the UDC Endpoint 0 Register. The Intel XScale processor can only read and write the FIFO at specific points in a control sequence.
Page 342: Udc Data Register 1
When the host sends a command, the UDC fills the FIFO with the command from the host and the Intel XScale processor reads the command from the FIFO when it arrives. The only time the Intel XScale processor may write the endpoint 0 FIFO is after a valid command from the host is received and it requires a transmission in response.
Page 343: Udc Data Register 2
Since it is double-buffered, up to two packets of data may be ready. Via direct read from the Intel XScale processor, the data can be removed from the UDC. If one packet is being removed and the packet behind it has already been received, the UDC will issue a NAK to the host the next time it sends an OUT packet to endpoint 2.
Page 344: Udc Data Register 4
Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via a direct read from the Intel XScale processor. If one packet is being removed and the packet behind it has already been received, the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint 4.
Page 345: Udc Data Register 5
UDC Data Register 6 (UDDR6) Endpoint 6 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be loaded via direct Intel XScale processor writes. Because it is double-buffered, up to two packets of data may be loaded for transmission.
Page 346: Udc Data Register 7
Since it is double-buffered, up to two packets of data may be ready. Via direct read from the Intel XScale processor, the data can be removed from the UDC. If one packet is being removed and the packet behind it has already been received, the UDC will issue a NAK to the host the next time it sends an OUT packet to endpoint 7.
Page 347: Udc Data Register 9
Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via a direct read from the Intel XScale processor. If one packet is being removed and the packet behind it has already been received, the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint 9.
Page 348: Udc Data Register 10
UDC Data Register 11 (UDDR11) Endpoint 11 is a double-buffered, bulk IN endpoint that is 64 bytes deep. Data can be loaded via direct Intel XScale processor writes. Because it is double-buffered, up to two packets of data may be loaded for transmission.
Page 349: Udc Data Register 12
Since it is double-buffered, up to two packets of data may be ready. Via direct read from the Intel XScale processor, the data can be removed from the UDC. If one packet is being removed and the packet behind it has already been received, the UDC will issue a NAK to the host the next time it sends an OUT packet to Endpoint 12.
Page 350: Udc Data Register 14
Because it is double-buffered, up to two packets of data may be ready. The data can be removed from the UDC via a direct read from the Intel XScale processor. If one packet is being removed and the packet behind it has already been received, the UDC issues a NAK to the host the next time it sends an OUT packet to Endpoint 14.
Page 351: Udc Data Register 15
(UDDR15) Endpoint 15 is an interrupt IN endpoint that is 8 bytes deep. Data must be loaded via direct Intel XScale processor writes. Because the USB system is a host-initiator model, the host must poll Endpoint 15 to determine interrupt conditions. The UDC cannot initiate the transaction.
Page 352: Usb 2.0 Host Controller
IXP46X network processors. The following is a partial list of supported features: • EHCI register interface • Host function • Low-speed interface • Full-speed interface The following is a partial list of USB 2.0 features not supported by the IXP45X/IXP46X network processors: • High-speed interface • Device function • OTG function The USB Host core is a standards-based “Serial Interface Engine”...
Page 353: Usb 2.0
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors USB software provides a uniform view of the system for all application software, hiding implementation details making application software more portable. It manages the dynamic attach and detach of peripherals.
Page 354: Feature List
The USB Host functionality for the IXP45X/IXP46X network processors is USB 2.0 specification-compliant but does not support the 480-Mbps, high-speed protocol. Feature List • Intel EHCI host controller. The USB host controller registers and data structures are ® compliant to Intel EHCI specification.
Page 355: Block Diagram
In this case, the system ® CPU is the Intel XScale Processor and the system memory is whatever system memory the USB block has its DMA engine pointed to. In this case, note that the USB 2.0 compliance is restricted to a legacy full-speed protocol and that the system...
Page 356 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 38. Periodic Schedule Organization Periodic Frame List Isochronous Transfer 1024, 512, or 256 Descriptor(s) elements Last periodic has End of List mark Operational Registers...
Page 357 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 39. Asynchronous Schedule Organization Operational Registers Bulk Control Queue Heads ASYNCLISTADDR B4020-01 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual...
Page 358: Hardware Model
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.6.3 Hardware Model 9.6.3.1 Block Diagram Figure 40. Block Diagram System Bus Slave Interface System Bus Master Interface Microprocessor DMA Engine Slave Interface • Bus Interface •...
Page 359: Microprocessor Interface
Two groups of registers exist in the interface. The USB host controller registers are compatible with the USB host controller registers defined in the Intel™ EHCI specification. ®...
Page 360: Dma Engine
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.6.3.3 DMA Engine Figure 42. DMA Engine Block Diagram Vusb_hs_dma_up_int To Microprocessor Interface DMA Microprocessor Registers Vusb_hs_dma_hst Vusb_hs_dma_traf Packet movement Host HS Vusb_hs_dma_ mem_arb_[ Device HS...
Page 361: Dual Port Ram Controller
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.6.3.4 Dual Port RAM Controller The Dual Port RAM Controller is used for context information and to build configurable FIFOs between the Protocol Engine block and the DMA controller. These FIFOs decouple the system processor memory bus request from the extremely tight timing required by the USB itself.
Page 362: Port Controller
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • The CRC5 and CRC16 CRC generator/checker circuits check and generate the CRC check fields for the token and data packets. • The data and handshake state machines generate any responses required on the USB and move the packet data through the dual port memory FIFOs to the DMA controller block.
Page 363: System Bus Interface
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.6.3.7 System Bus Interface The USB Host core interfaces to the system memory and processing resources using an AMBA AHB. This provides the features required for high performance/high clock frequency systems including: •...
Page 364: Detailed Register Descriptions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 121. Configuration Controls (Sheet 2 of 2) Constant Description Supported Values 0=Normal Bandwidth Testing 1=Bandwidth Starved Controls the testing of the core. This constant should...
Page 365: Interface Register Sets
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 122. Register Legend Attribute Legend Attribute Legend Read/Set Write Only Read/Write Not Accessible Normal Read Normal Read RW1C RW1S Write ‘1’ to clear Write ‘1’ to set Slave accesses from the controlling processor enables access to the configuration, control, and status registers.
Page 366: Configuration, Control And Status Register Set
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Configuration, Control and Status Register Set Table 124. Host Capability Registers (Sheet 1 of 2) Single Size Port Offset Mnemonic Register Name (Bytes) Host (SPH)
Page 367: Identification Registers
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 124. Host Capability Registers (Sheet 2 of 2) Single Size Port Offset Mnemonic Register Name (Bytes) Host (SPH) Configured Flag 180h CONFIGFLAG ÷ Register...
Page 368: Hwhost
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) PHYM...
Page 369: Hwtxbuf
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) DEVEP Table 128.
Page 370: Host Capability Registers
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 130. HWRXBUF – RX Buffer Hardware Parameters Field Description (Reserved) These bits are reserved and should be zero. RXADD VUSB_HS_RX_ADD RXBURST VUSB_HS_RX_BURST 9.11 Host Capability Registers Host Capability registers specify the software limits, restrictions, and capabilities of the host controller implementation.
Page 371: Hccparams - Ehci Compliant
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) N_TT...
Page 372: Reserved Register #1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Size: 32 bits This register identifies multiple mode control (time-base bit functionality) addressing capability. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 373: Dccparams - Device Control Capability Parameters
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Attribute: Read Only Size: 32 bits These fields describe the overall host capability of the controller. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) Table 133.
Page 374: August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 134. USBCMD – USB Command Register (Sheet 1 of 2) Field Description These bits are reserved and should be zero. (Reserved) Interrupt Threshold Control —Read/Write. Default 08h. The system software uses this field to set the maximum rate at which the host controller will issue interrupts.
Page 375: Usbsts
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 134. USBCMD – USB Command Register (Sheet 2 of 2) Field Description Periodic Schedule Enable— Read/Write. Default Ob. This bit controls whether the host controller skips processing the Periodic Schedule.
Page 376: Usbsts - Usb Status
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) AS PS Table 135.
Page 377: Usbintr
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 135. USBSTS – USB Status (Sheet 2 of 2) Field Description Port Change Detect — R/WC. The Host Controller sets this bit to a one when on any port a Connect Status occurs, a Port Enable/Disable Change occurs, or the Force Port Resume bit is set as the result of a J-K transition on the suspended port.
Page 378: Frindex
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 136. USBINTR – USB Interrupt Enable Interrupt Field Description Source When this bit is a one, and the Frame List Rollover bit in the USBSTS register is a one, the host controller will issue an interrupt.
Page 379: Ctrldssegment
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 137. FRINDEX – USB Frame Index Field Description (Reserved) These bits are reserved and should be zero. Frame Index. The value, in this register, increments at the end of each time frame (e.g. micro-frame). Bits [N: 3] are used for the Frame List current index.
Page 380: Asynclistaddr; Endpointlistaddr
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 138. PERIODICLISTBASE - Host Controller Frame List Base Address Field Description Base Address (Low). These bits correspond to memory address signals [31:12], respectively. BASEADR Only used by the host controller.
Page 381: Txfilltuning
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 140. BURSTSIZE - Host Controller Embedded TT Async. Buffer Status Field Description (Reserved) These bits are reserved and their value has no effect on operation.
Page 382: 11Portscx
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Default Value: 0x00000001 Attribute: Read Only Size: 32 bits This register is not used in this implementation. A read from this register returns a constant of a 00000001h to indicate that all port routings default to this host controller.
Page 383: Portscx - Port Status Control[1:8]
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 141. PORTSCx - Port Status Control[1:8] (Sheet 1 of 4) Field Description Parallel Transceiver Select – Read/Write. This register bit is used in conjunction with the configuration constant VUSB_HS_PHY_MODE to control which parallel transceiver interface is selected.
Page 384 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 141. PORTSCx - Port Status Control[1:8] (Sheet 2 of 4) Field Description Wake on Disconnect Enable (WKDSCNNT_E) — Read/Write. Default=0b. Writing this bit to a one enables the port to be sensitive to device disconnects as wake-up events.
Page 385 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 141. PORTSCx - Port Status Control[1:8] (Sheet 3 of 4) Field Description High-Speed Port — Read Only. Default = 0b. When the bit is one, the host connected to the port is in high-speed mode and if set to zero, the host connected to the port is not in a high-speed mode.
Page 386 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 141. PORTSCx - Port Status Control[1:8] (Sheet 4 of 4) Field Description Over-current Change—R/WC. Default=0. 1=This bit gets set to one when there is a change to Over-current Active.
Page 387: 12Usbmode
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.12.12 USBMODE Address: Base + 1A8h Default Value: 0x00000000 00000003h (host mode) Attribute: R/WO, Read Only Size: 32 bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 (Reserved) Table 142.
Page 388: Periodic Frame List
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller The periodic frame list is the root of all periodic (isochronous and interrupt transfer type) support for the host controller interface. The asynchronous list is the root for all the bulk and control transfer type support.
Page 389: Typ Field Value Definitions
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The least significant bit is the T-Bit (bit 0). When this bit is set to a one, the host controller will never use the value of the frame list pointer as a physical memory pointer.
Page 390: Asynchronous List Queue Head Pointer
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 45. Periodic Schedule Organization Periodic Frame List Isochronous Transfer 1024, 512, or 256 Descriptor(s) elements Last periodic has End of List mark Operational Registers...
Page 391: Isochronous (High-Speed) Transfer Descriptor (Itd)
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 46. Asynchronous Schedule Organization Operational Registers Bulk Control Queue Heads ASYNCLISTADDR B4020-01 The Asynchronous list is a simple circular list of queue heads as shown in...
Page 392: Next Link Pointer
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 47. Isochronous Transaction Descriptor (iTD) B4464-01 Note: These fields may be modified by the host controller if the I/O field indicates an OUT. 9.13.3.1 Next Link Pointer The first DWord of an iTD is a pointer to the next schedule data structure.
Page 393: Next Schedule Element Pointer
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 144. Next Schedule Element Pointer Description Link Pointer (LP). These bits correspond to memory address signals [31:5], respectively. This 31:5 field points to another Isochronous Transaction Descriptor (iTD/siTD) or Queue Head (QH).
Page 394: Itd Buffer Page Pointer List (Plus)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 145. iTD Transaction Status and Control (Sheet 2 of 2) Description Interrupt On Complete (IOC). If this bit is set to one, it specifies that when this transaction completes, the Host Controller should issue an interrupt at the next interrupt threshold.
Page 395: Split Transaction Isochronous Transfer Descriptor (Sitd)
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 148. iTD Buffer Pointer Page 2 (Plus) Description Buffer Pointer. This is a 4K aligned pointer to physical memory. Corresponds to memory 31:12 address bits [31:12].
Page 396: Endpoint And Transaction Translator Characteristics
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 150. Next Link Pointer Description Next Link Pointer (LP). This field contains the address of the next data object to be 31:5 processed in the periodic list and corresponds to memory address signals [31:5], respectively.
Page 397: Micro-Frame Schedule Control
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 152. Micro-Frame Schedule Control Description 31:16 (Reserved). This field reserved for future use. It should be zero. Split Completion Mask (μFrame C-Mask). This field (along with the Active and SplitX- state fields in the Status byte) is used to determine during which micro-frames the host controller should execute complete-split transactions.
Page 398: Sitd Buffer Pointer List (Plus)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 153. siTD Transfer Status and Control (Sheet 2 of 2) Description Missed Micro-Frame. The host controller detected that a host-induced hold- off caused the host controller to miss a required complete-split transaction.
Page 399: Queue Element Transfer Descriptor (Qtd)
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 155. siTD Back Link Pointer Description 31:5 siTD Back Pointer. This field is a physical memory pointer to a siTD. (Reserved). This field is reserved for future use. It should be zero.
Page 400: Qtd Next Element Transfer Pointer (Dword 0)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.13.5.1 Next qTD Pointer The first DWord of an element transfer descriptor is a pointer to another transfer element descriptor. Table 156. qTD Next Element Transfer Pointer (DWord 0) Description Next Transfer Element Pointer.
Page 401: Qtd Token (Dword 2)
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 158. qTD Token (DWord 2) (Sheet 1 of 2) Description Data Toggle. This is the data toggle sequence bit. The use of this bit depends on the setting of the Data Toggle Control bit in the queue head.
Page 402 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 158. qTD Token (DWord 2) (Sheet 2 of 2) Description SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt the queue head is non-zero.) transfer type, e.g. μFrame S-mask field in (Reserved) Status.
Page 403: Qtd Buffer Page Pointer List
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.13.5.4 qTD Buffer Page Pointer List The last five DWords of a queue element transfer descriptor is an array of physical memory address pointers. These pointers reference the individual pages of a data buffer.
Page 404: Queue Head
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.13.6 Queue Head Figure 50. Queue Head Structure Layout B4467-01 9.13.6.1 Queue Head Horizontal Link Pointer The first DWord of a Queue Head contains a link pointer to the next data object to be processed after any required processing in this queue has been completed, as well as the control bits defined below.
Page 405: Endpoint Capabilities/Characteristics
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 160. Queue Head DWord 0 Description Queue Head Horizontal Link Pointer (QHLP). This field contains the address of the next data 31:5 object to be processed in the horizontal list and corresponds to memory address signals [31:5], respectively.
Page 406: Endpoint Capabilities: Queue Head Dword 2
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 161. Endpoint Characteristics: Queue Head DWord 1 (Sheet 2 of 2) Description Data Toggle Control (DTC). This bit specifies where the host controller should get the initial data toggle on an overlay transition.
Page 407: Transfer Overlay
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 162. Endpoint Capabilities: Queue Head DWord 2 (Sheet 2 of 2) Description Hub Addr. This field is ignored by the host controller unless the EPS field indicates a full-or low- speed device.
Page 408: Periodic Frame Span Traversal Node (Fstn)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 164. Host-Controller Rules for Bits in Overlay (DWords 5, 6, 8 and 9) DWord Description Nak Counter (NakCnt)μRW. This field is a counter the host controller decrements whenever a transaction for the endpoint associated with this queue head results in a Nak or Nyet response.
Page 409: Fstn Back Path Link Pointer
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 165. FSTN Normal Path Pointer Signals Description Normal Path Link Pointer (NPLP). This field contains the address of the next data object to be 31:5 processed in the periodic list and corresponds to memory address signals [31:5], respectively.
Page 410: Host Controller Initialization
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.14.1 Host Controller Initialization After initial power-on or HCReset (hardware or via HCReset bit in the USBCMD register), all of the operational registers will be at their default values, as illustrated in Table 167, “Default Values of Operational Register Space”...
Page 411: Port Routing And Control
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.2 Port Routing and Control A USB 2.0 Host controller is comprised of one high-speed host controller, which implements the EHCI programming interface and 0 to N USB 1.1 companion host controllers.
Page 412: Port Routing Control Via Ehci Configured (Cf) Bit
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller following sections. The USB 2.0 host controller must be implemented as a multi- function PCI device if the implementation includes companion controllers. The companion host controllers’ function numbers must be less than the EHCI host controller function number.
Page 413: Port Routing Control Via Portowner And Disconnect Event
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.2.2 Port Routing Control via PortOwner and Disconnect Event Manipulating the port routing via the CF-bit is an extreme process and not intended to be used during normal operation. The normal mode of port ownership transferal is on the granularity of individual ports using the Port Owner bit in the EHCI HC’s PORTSC...
Page 414: Example Port Routing State Machine
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller the EHCI controller. The companion HC stack detects the disconnect and acknowledges as it would in an ordinary standalone implementation. Subsequent connects will be detected by the EHCI port register and the process will repeat.
Page 415: Port Power
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.2.4 Port Power The Port Power Control (PPC) bit in the HCSPARAMS register indicates whether the USB 2.0 host controller has port power control (See Section 9.11.3, “HCSPARAMS –...
Page 416: Suspend/Resume
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • Over-current Change bits are set to a one. On every transition of the Over-current Active bit the host controller will set the Over-current Change bit to a one. Software sets the Over-current Change bit to a zero by writing a one to this bit.
Page 417 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors several micro-frames of activity on the port until the host controller evaluates the Suspend bit. The host controller must evaluate the Suspend bit at least every frame boundary.
Page 418: Schedule Traversal Rules
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 170. Behavior During Wake-Up Events Device State Port Status and Signaling Type Signaled Port Response Port disabled, resume K-State received No Effect Resume reflected downstream on signaled port. Force Port Port suspended, Resume K-State received Resume status bit in PORTSC register is set to a one.
Page 419: Derivation Of Pointer Into Frame List Array
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The end of the periodic schedule is identified by a next link pointer of a schedule data structure having its T-bit set to a one. When the host controller encounters a T-Bit set to a one during a horizontal traversal of the periodic list, it interprets this as an End-Of- Periodic-List mark.
Page 420: Example: Preserving Micro-Frame Integrity
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.14.4.1 Example: Preserving Micro-Frame Integrity One of the requirements of a USB host controller is to maintain Frame Integrity. This means that the HC must preserve the micro-frame boundaries. For example: SOF packets must be generated on time (within the specified allowable jitter), and High- speed EOF1,2 thresholds must be enforced.
Page 421: Best Fit Approximation
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 56. Best Fit Approximation 7000 6000 5000 Byte Transactions that Times will be started 4000 3000 2000 Goal is to minimize area under this curve...
Page 422 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 171. Example Worst-Case Transaction Timing Components (Sheet 2 of 2) Component Byte Time Explanation Time Time for packet initiator (Host) to see the beginning of a Turnaround time 90.125...
Page 423: Periodic Schedule Frame Boundaries Versus Bus Frame Boundaries
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.5 Periodic Schedule Frame Boundaries versus Bus Frame Boundaries The USB Specification Revision 2.0 requires that the frame boundaries (SOF frame number changes) of the high-speed bus and the full- and low-speed bus(s) below USB 2.0 hubs be strictly aligned.
Page 424: Relationship Of Periodic Schedule Frame Boundaries To Bus Frame Boundaries
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 58. Relationship of Periodic Schedule Frame Boundaries to Bus Frame Boundaries Interface Data Interface Data Structure Structure B4501-01 H-Frame boundaries for the host controller correspond to increments of FRINDEX[13:3].
Page 425: Periodic Schedule
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 172. Operation of FRINDEX and SOFV (SOF Value Register) (Sheet 2 of 2) Current Next 100b 101b 101b 110b 110b 111b Note: Where [F] = [13:3]; [μF] = [2:0] 9.14.6...
Page 426: Managing Isochronous Transfers Using Itds
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 59. Example Periodic Schedule Periodic Frame List 1024, 512, or 256 elements Isochronous Transfer Descriptor(s) Last Periodic has End of List mark Interrupt Queue...
Page 427 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors When the indexed active bit is a one the host controller continues to parse the iTD. It stores the indexed transaction description and the general endpoint information (device address, endpoint number, maximum packet size, etc.).
Page 428: Software Operational Model For Itds
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • The endpoint is an OUT and Transaction X Length goes to zero before all the Mult transactions have executed (ran out of data), or •...
Page 429: Example Association Of Itds To Client Request Buffer
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 60. Example Association of iTDs to Client Request Buffer Client Request USB Xact Information Frame List Frame i Frame i+1 Frame I+2 Frame i+n...
Page 430: Asynchronous Schedule
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller The iTD and siTD data structures each describe 8 micro-frames worth of transactions. The host controller is allowed to cache one (or more) of these data structures in order to reduce memory traffic.
Page 431: Adding Queue Heads To Asynchronous Schedule
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors determine when the asynchronous schedule has made the desired transition. Software must not modify the Asynchronous Schedule Enable bit unless the value of the Asynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status bit.
Page 432: Removing Queue Heads From Asynchronous Schedule
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller When inserting a queue head into an active list, software must ensure that the schedule is always coherent from the host controllers' point of view. This means that the system software must ensure that all queue head pointer fields are valid.
Page 433 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors UnlinkQueueHead (pQHeadPrevious, pQueueHeadToUnlink, pQHeadNext) -- Requirement: all inputs must be properly initialized. -- pQHeadPrevious is a pointer to a queue head that -- references the queue head to remove...
Page 434: Generic Queue Head Unlink Scenario
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller lightweight handshake that is used by software as a key that it can free (or reuse) the memory associated the data structures it has removed from the asynchronous schedule.
Page 435: Empty Asynchronous Schedule Detection
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Software may re-use the memory associated with the removed queue heads after it observes the Interrupt on Async Advance status bit is set to a one, following assertion of the doorbell.
Page 436: Example State Machine For Managing Asynchronous Schedule Traversal
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller asynchronous schedule traversal is because of empty list detection, it is mandatory the host controller implement a 'waking' method to resume traversal of the asynchronous schedule.
Page 437: Asynchronous Schedule State Machine Transition Actions
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 173. Asynchronous Schedule State Machine Transition Actions Action Action Description Label On detection of the empty list, the host controller sets the AsynchronousTraversalSleepTimer to AsyncSchedSleepTime.
Page 438: Asynchronous Schedule Traversal: Start Event
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 174. Typical Low- /Full-Speed Transaction Times (Sheet 2 of 2) Footprint Transaction Attributes Description (Time) Speed ~12 µs Approximate typical for 8-byte bulk/control (i.e. setup)
Page 439: Operational Model For Nak Counter
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.9 Operational Model for Nak Counter This section describes the operational model for the NakCnt field defined in a queue head (see Section 9.13.6, “Queue Head” on page 404).
Page 440: Nak Count Reload Control
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Any time the host controller begins a new traversal of the Asynchronous Schedule, a Start Event is assumed, see “Asynchronous Schedule Traversal: Start Event” on page 438.
Page 441: 10Managing Control/Bulk/Interrupt Transfers Via Queue Heads
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.9.1.2 Do Reload This state is entered from the Wait for List Head state when the host controller fetches a queue head with the H-bit set to a one. While in this state, the host controller will perform nak counter reloads for every queue head visited that has a non-zero nak reload value (RL) field.
Page 442: Host Controller Queue Head Traversal State Machine
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 65. Host Controller Queue Head Traversal State Machine S t a r t Halted .or. !Active .AND. Ibit Fetch QH !Active Advance !Active .AND. !Halted .AND.
Page 443: 1Fetch Queue Head
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors • For the very first use of a queue head, software may zero-out the queue head transfer overlay, then set the Next qTD Pointer field value to reference a valid qTD.
Page 444: 3Execute Transaction
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • If the EPS field indicates the endpoint is a high-speed endpoint, the Ping state field is preserved by the host controller. The value of this field is not changed as a result of the overlay.
Page 445 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors mandatory for interrupt queue heads. Software should ensure that the Mult field is set appropriately for the transfer type. The pre-conditions evaluated are: — The host controller determines whether there is enough time in the micro- frame to complete this transaction (see Section 9.14.4.1, “Example: Preserving...
Page 446 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller After the transaction has finished and the host controller has completed the post processing of the results (advancing the transfer state and possibly NakCnt, the host controller writes back the results of the transaction to the queue head’s overlay area in...
Page 447 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.10.3.1 Halting a Queue Head A halted endpoint is defined only for the transfer types that are managed via queue heads (control, bulk and interrupt). The following events indicate that the endpoint has...
Page 448: Actions For Park Mode, Based On Endpoint Response And Residual Transfer State
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller The host controller must apply park mode to queue heads whose EPS field indicates a high-speed endpoint. The maximum number of consecutive bus transactions a host controller may execute on a high-speed queue head is determined by the value in the Asynchronous Schedule Park Mode Count field in the USBCMD register.
Page 449: 4Write Back Qtd
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 176. Actions for Park Mode, Based on Endpoint Response and Residual Transfer State (Sheet 2 of 2) Transfer State after Transaction Endpoint Action Response...
Page 450: Example Mapping Of Qtd Buffer Pointers To Buffer
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller a full 4K page. The final portion, which may only be large enough to occupy a portion of a page, must start at the top of the page and be contiguous within that page.
Page 451: 7Adding Interrupt Queue Heads To The Periodic Schedule
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors pointer is the page 1 pointer and Current Offset has rolled to one, and both are written back to the overlay area. The transactions continue for the rest of the buffer, with the host controller automatically moving to the next page pointer (i.e.
Page 452: 11Ping Control
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.14.11 Ping Control USB 2.0 defines an addition to the protocol for high-speed devices called Ping. Ping is required for all USB 2.0 High-speed bulk and control endpoints. Ping is not allowed for a split-transaction stream.
Page 453: 12Split Transactions
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors initializes a queue head. The host controller preserves the Ping State bit across all queue advancements. This means that when a new qTD is written into the queue head overlay area, the previous value of the Ping State bit is preserved.
Page 454: Host Controller Asynchronous Schedule Split-Transaction State Machine
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 67. Host Controller Asynchronous Schedule Split-Transaction State Machine Endpoint Halt Endpoint Halt Nyet CERR goes CERR goes to zero to zero Stall Decrement Error...
Page 455: 2Split Transaction Interrupt
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors executing from the Asynchronous schedule, it must begin executing from this queue head. If another start-split (for some other endpoint) is sent to the transaction translator before the complete-split is really completed, the transaction translator could dump the results (which were never delivered to the host).
Page 456: Split Transaction, Interrupt Scheduling Boundary Conditions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.14.12.2.1 Split Transaction Scheduling Mechanisms for Interrupt Full- and low-speed Interrupt queue heads have an EPS field indicating full- or low- speed and have a non-zero S-mask field. The host controller can detect this combination of parameters and assume the endpoint is a periodic endpoint.
Page 457: General Structure Of Ehci Periodic Schedule Utilizing Interrupt Spreading
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Frame to B-Frame alignment requires that the queue head be reachable from consecutive periodic frame list locations. System software cannot build an efficient schedule that satisfies this requirement unless it uses FSTNs.
Page 458: Host Controller Operational Model For Fstns
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • SplitXState. This is a single bit residing in the Status field of a queue head (see Table 158, “qTD Token (DWord 2)” on page 401).
Page 459: Example Host Controller Traversal Of Recovery Path Via Fstns
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors considered for execution of bus transactions. The host controller continues executing in Recovery Path mode until it encounters a Restore FSTN or it determines that it has reached the end of the micro-frame (see details in the list below).
Page 460: Software Operational Model For Fstns
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller In frame N (micro-frames 0-7), for this example, the host controller will traverse all of the schedule data structures utilizing the Normal Path Link Pointers in any FSTNs it encounters.
Page 461 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors offset N, then the FSTN’s Back Path Link Pointer must reference a queue head that is reachable from frame list offset N-1. Software should make the schedule as efficient as possible. What this means in this context is that software should have no more than one Save-Place FSTN reachable in any single frame.
Page 462 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller As with asynchronous Full- and Low-speed endpoints, a split-transaction state machine is used to manage the split transaction sequence. Aside from the fields defined in the queue head for scheduling and tracking the split transaction, the host controller calculates one internal mechanism that is also used to manage the split transaction.
Page 463: Split Transaction State Machine For Interrupt
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 71. Split Transaction State Machine for Interrupt (QH.S-Mask and cMicroFrameBit) (QH.S-Mask and cMicroFrameBit) Do_Start Active • Issue start-split transaction Split Queue • Tag QH with frame number according...
Page 464 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller If the result is non-zero, then the host controller will issue a start-split transaction. If the PIDCode field indicates an IN transaction, the host controller must zero-out the QH.S-bytes field.
Page 465 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors End if End If -- If the C-prog-mask already has a one in this bit position, -- then an aliasing -- error has occurred. It will probably get caught by the...
Page 466 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller update any transfer state (except for C-prog-mask and FrameTag) and stay in this state. The host controller must not adjust CErr on this response. • Transaction Error (XactErr). Timeout, data CRC failure, etc. The CErr field is decremented and the XactErr bit in the Status field is set to a one.
Page 467: Interrupt In/Out Do Complete Split State Execution Criteria
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 180. Interrupt IN/OUT Do Complete Split State Execution Criteria Condition Action Description not(A) Neither a start nor complete-split is scheduled for the current micro-frame.Host controller Ignore QHD should continue walking the schedule.
Page 468: 3Split Transaction Isochronous
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller It is imperative that System software must not update these masks to new values in the midst of a split transaction. In order to avoid any race conditions with the update, the EHCI host controller provides a simple assist to system software.
Page 469: Split Transaction, Isochronous Scheduling Boundary Conditions
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors complete-splits (respectively). The H-Frame boundaries are marked with a large, solid bold vertical line. The B-Frame boundaries are marked with a large, bold, dashed line.
Page 470 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • Case 2b: This case can only occur for a very large isochronous IN. It is the only allowed scenario where a start-split and complete-split for the same endpoint can occur in the same micro-frame.
Page 471: Sitd Scheduling Boundary Examples
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 73. siTD Scheduling Boundary Examples Full-Speed Case 1 Case 2a Case 2b Transaction B-Frame B-Frame B-Frame B-Frame H-Frame H-Frame H-Frame H-Frame siTD siTD Back Pointer...
Page 472 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller In similar kind to interrupt split-transactions, the portions of the split transaction protocol must execute in the micro-frames they are scheduled. The queue head data structure used to manage full- and low-speed interrupt has several mechanisms for tracking when portions of a transaction have occurred.
Page 473 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Transfer to zero signals the end of the transfer and results in setting of the Active bit to zero. However, in this case, the result has not been delivered by the Transaction Translator and the host must continue with the next complete-split transaction to extract the residual transaction state.
Page 474: Split Transaction State Machine For Isochronous
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Figure 74. Split Transaction State Machine for Isochronous Active = 1b Not Active siTD.S-mask & cMicroFrameBit .and. Active = 0b direction.eq.OUT Active = 0b OUT Split...
Page 475: Initial Conditions For Out Sitd's Tp And T-Count Fields
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors T-Count is always initialized to the number of start-splits for the current frame. TP is always initialized to the first required transaction position identifier. The scheduling boundary case (see Figure 73, “siTD Scheduling Boundary Examples”...
Page 476 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller If the host experiences hold-offs that cause the host controller to skip start-split transactions for an OUT transfer, the state of the transfer will not progress appropriately.
Page 477 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Return rvalue End Algorithm If Test A is true and FRINDEX[2:0] is zero or one, then this is a case 2a or 2b scheduling boundary (see Figure 72, “Split Transaction, Isochronous Scheduling...
Page 478: Summary Sitd Split Transaction State
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller set in the Status field because this is essentially a skipped transaction. The transaction translator must have responded to all the scheduled complete-splits with NYETs, meaning that the start-split issued by the host controller was not received.
Page 479 ® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors In order to access siTD , the host controller reads on-chip the siTD referenced from siTD .Back Pointer. The host controller must save the entire state from siTD while processing siTD .
Page 480: Example Case 2A - Software Scheduling Sitds For An In Endpoint
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller Table 184. Example Case 2a - Software Scheduling siTDs for an IN Endpoint siTD Micro-Frames Initial SplitXState Masks S-Mask Do Start Split C-Mask S-Mask Do Complete Split...
Page 481: 13Host Controller Pause
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Active bit to a zero. It returns to the state of siTD and changes its SplitXState to Do Start Split. At this point, the host controller is prepared to execute start-splits for siTDX+2 when it reaches micro-frame 4.
Page 482: 15Interrupts
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • Place all enabled root ports into the suspended state by setting the Suspend bit in each appropriate PORTSC register to a one. • Set the Run/Stop bit in the USBCMD register to a zero and wait for the HCHalted bit in the USBSTS register, to transition to a one.
Page 483: Summary Of Transaction Errors
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors call (DPC) which will execute later. The DPC routine processes the results of the schedule execution. The precise mechanisms used are beyond the scope of this document.
Page 484: Data Buffer Error
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller queue head (see ). Maximum Length is defined as the “Halting a Queue Head” on page 447 minimum of Total Bytes to Transfer and Maximum Packet Size. The CErr field is not decremented for a packet babble condition (only applies to queue heads).
Page 485: 2Host Controller Event Interrupts
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.14.15.1.3 Short Packet Reception of a data packet that is less than the endpoint’s Max Packet size during Control, Bulk or Interrupt transfers signals the completion of the transfer. Whenever a short packet completion occurs during a queue head execution, the USBINT bit in the USBSTS register is set to a one.
Page 486: Ehci Deviation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller — Host System Error bit is to a one. — HCHalted bit is set to a one. • If the Host System Error Enable bit in the USBINTR register is a one, then the host controller will issue a hardware interrupt.
Page 487: Capability Registers
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors the system, the transaction translator function normally associated with a high speed hub has been implemented within the DMA and Protocol engine blocks. The embedded...
Page 488: Data Structures
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.15.1.4 Data Structures The same data structures used for FS/LS transactions though a HS hub are also used for transactions through the Root hub with sm embedded Transaction Translator. Here it...
Page 489: Condition Vs. Emulate Tt Response
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Once periodic transfers are exhausted, any stored asynchronous transfer will be moved. Asynchronous transfers are opportunistic in that they execute whenever possible and their operation is not tied to H-frame and B-frame boundaries with the exception that an asynchronous transfer cannot babble through the SOF (start of B- frame 0.)
Page 490: Device Operation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller • Abort of pending complete-splits — EOF — Idle for more than 4 micro-frames USB 2.0 – 11.18.[7-8] • Transaction tracking for up to 16 data pipes.
Page 491: Sof Interrupt
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 9.15.2.3 SOF Interrupt This SOF Interrupt used for device mode is shared as a free-running, 125-us interrupt for host mode. EHCI does not specify this interrupt but it has been added for convenience and as a potential software time base.
Page 492: Port Test Mode
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller 9.15.4.2.2 Port Speed Detection After the port change interrupt indicates that a port is enabled, the EHCI stack should determine the port speed. Unlike the EHCI implementation which will re-assign the port owner for any device that does not connect at High-Speed, this host controller supports direct attach of non High-Speed devices.
Page 493: Usb Power States
® ® USB 2.0 Host Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors test_packet[42]=0xFB; test_packet[43]=0xFD; test_packet[44]=0xFC; test_packet[45]=0x7E; test_packet[46]=0xBF; test_packet[47]=0xDF; test_packet[48]=0xEF; test_packet[49]=0xF7; test_packet[50]=0xFB; test_packet[51]=0xFD; test_packet[52]=0x7E; 5. Write Run/Stop and Asynchronous Schedule Enable (USBCMD Register) to their active states. Test packets will begin being sent continuously and SOFs will be suppressed.
Page 494 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller packet processing and/or control block processing will cease, the error bit will be set, and an interrupt generated. The only recourse for an AHB error is a software commanded USB bus reset.
Page 495: Pci Controller
When the PCI Controller is configured as a host, an internal PCI arbiter may be utilized to allow up to four devices to be connected to the IXP45X/IXP46X network processors without the need for an external arbiter. However, even though the internal PCI arbiter exists, the internal PCI arbiter is not required to be used when the PCI controller is configured in host or for that matter option mode of operation.The arbiter functionality...
Page 496: Pci Bus Configured As A Host
Network Processor PCI Bused Signals Host Processor PCI_REQ PCI_GNT PCI-to-VGA Controller B4276-02 The IXP45X/IXP46X network processors PCI Controller block diagram is shown in Figure ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Develepor’s Manual August 2006...
Page 497: Pci Controller Block Diagram
PCI bus and the South AHB. The external PCI bus has both a target and an initiator controller that interfaces to the PCI bus. When an external PCI device wants to use the IXP45X/IXP46X network processors as the target of a PCI transfer, the PCI Controller Target interface will interpret the data and forward the appropriate information (data/address/control) to the Target interface ®...
Page 498: Pci Target Interface Supported Commands
Memory Write and Invalidate Converted To Memory Write When the IXP45X/IXP46X network processors want to use an external PCI device as the target of a PCI transfer, the PCI Controller Initiator interface will be used to generate the appropriate PCI bus cycles and forward the information to the PCI bus.
Page 499: Pci Initiator Interface Supported Commands
Initiator Data FIFOs. The Initiator Data FIFOs are eight words deep. Table 190 lists the supported PCI transaction types produced by the PCI Controller Initiator Interface of the IXP45X/IXP46X network processors. Table 190. PCI Initiator Interface Supported Commands PCI Byte Enables...
Page 500: List Of Features
PCI Configuration Space when the IXP45X/IXP46X network processors are configured as an Option. The PCI Configuration Space may be accessed by the Intel XScale processor or the PCI bus but never by both at the same time.
Page 501: Pci Controller Configured As Host
Expansion Bus Address Bus bit 2 at the de-assertion of the reset signal supplied to the IXP45X/IXP46X network processors. The PCI Controller Control and Status Register (PCI_CSR) bit 1 captures the logic level contained on Expansion Bus Address Bus bit 2 at the de-assertion of reset.
Page 502: Type 0 Configuration Address Phase
Bus Segment Number = Decodes one of 256 possible bus segments per PCI Bus (refer to the PCI Local Bus Specification, Rev. 2.2) Configuration cycles will be produced by the IXP45X/IXP46X network processors using four 32-bit Configuration and Status Registers referred to as the Non-Pre-fetch Registers.
Page 503: Example: Generating A Pci Configuration Write And Read
Only bits (31:26) would be written. Now, the IXP45X/IXP46X network processors must read Base Address Register 0 to determine the Address Space, Address space type (memory or I/O), and any limitations to reading this address space.
Page 504: Pci Controller Configured As Option
PCI host and successfully configured the PCI bus. PCI memory and PCI I/O transaction can now take place. For more detail on generating PCI Memory and PCI I/O transactions using the IXP45X/ IXP46X network processors, see “PCI Controller Functioning as Bus Initiator” on page 512.
Page 505: Initializing Pci Controller Configuration And Status Registers For Data Transactions
IXP45X and Intel IXP46X Product Line of Network Processors If the IXP45X/IXP46X network processors are configured as an option, an external PCI Host will want to access the PCI Configuration Space of the IXP45X/IXP46X network processors. The PCI Host will complete these accesses using PCI Configuration Cycles.
Page 506 South AHB to the address of the PCI Bus. When the IXP45X/IXP46X network processors are the target of a PCI bus transaction, the values written or read by external PCI Bus Initiators using the Base Address Registers contained within the IXP45X/IXP46X network processors must be translated to an address location within the processors.
Page 507: Example: Ahb Memory Base Address Register, Ahb I/O Base Address Register, And Pci Memory Base Address Register
A1 located in the fourth byte from the right of the PCI Address = 0xA100402C. 4. Next, an external PCI device initiates a PCI bus transfer to BAR3 of the IXP45X/ IXP46X network processors. The PCI address looks like the following: PCI Address = 0xA3004014.
Page 508: Example: Pci Memory Base Address Register And South-Ahb Translation
16-Mbyte window from South AHB address 0x4B000000 to 0x4BFFFFFF. The PCI Memory Base Address Register (PCI_PCIMEMBASE) register is used to determine the upper eight PCI address bits when the IXP45X/IXP46X network processors access the memory spaces of external Targets on the PCI bus. 10.2.4.2...
Page 509: Initializing The Pci Controller Configuration Registers
Intel XScale processor when the IXP45X/IXP46X network processors are configured as the PCI host. The PCI Base Address Registers must be initialized by an external PCI device when the IXP45X/IXP46X network processors are configured as a PCI option.
Page 510 Retry Timeout/TRDY Timeout (PCI_RTOTTO) Register is 0x0000AB80. Notice that only one byte of data was manipulated. Table 192 shows the PCI Byte Enables Byte Lane Mapping (accesses to the PCI Configuration Space from within the IXP45X/IXP46X network processors) when using the CRP access mechanism. ® ®...
Page 511: Pci Byte Enables Using Crp Access Method
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 192. PCI Byte Enables Using CRP Access Method PCI_CRP_AD_CBE(23:20 PCI_CRP_WDATA PCI_CRP_WDATA PCI_CRP_WDATA PCI_CRP_WDATA [31:24] [24:16] [15:8] [7:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000...
Page 512: Pci Controller South Ahb Transactions
512. 10.2.7 PCI Controller Functioning as Bus Initiator The IXP45X/IXP46X network processors can be used to initiate PCI transactions in one of three ways: • Using the Non-Pre-fetch Registers — described in “PCI Controller Configured as Host” on page 501 The Non-Pre-fetch Registers allow various single 32-bit word PCI Cycles to be produced as well as 8 and 16 bit transfers.
Page 513: Initiated Pci Type-0 Configuration Read Cycle
10.2.7.1 Initiated Type-0 Read Transaction The following transaction is a PCI Configuration Read Cycle initiated from the IXP45X/ IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/IXP46X network processors.
Page 514: Initiated Pci Type-0 Configuration Write Cycle
10.2.7.3 Initiated Type-1 Read Transaction The following transaction is a PCI Configuration Read Cycle initiated from the IXP45X/ IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/IXP46X network processors.
Page 515: Initiated Pci Type-1 Configuration Read Cycle
Initiated Type-1 Write Transaction The following transaction is a PCI Configuration Write working-site cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/IXP46X network processors.
Page 516: Initiated Pci Type-1 Configuration Write Cycle
The following transaction is a PCI Memory Read Cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/ IXP46X network processors. The transaction is initiated to address location hexadecimal 0x00000014.
Page 517: Initiated Pci Memory Write Cycle
The following transaction is a PCI I/O Read Cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/ IXP46X network processors. The transaction is initiated to address location hexadecimal 0x00000010.
Page 518: Initiated Pci I/O Read Cycle
The following transaction is a PCI I/O Write Cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/ IXP46X network processors. The transaction is initiated to address location hexadecimal 0x00000015.
Page 519: Initiated Pci I/O Write Cycle
Initiated Burst Memory Read Transaction The following transaction is a two word bursting PCI Memory Read Cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/IXP46X network processors.
Page 520: Initiated Pci Burst Memory Read Cycle
Initiated Burst Memory Write Transaction The following transaction is a two word bursting PCI Memory Write Cycle initiated from the IXP45X/IXP46X network processors. This diagram is to understand the inner workings of PCI transfers and may not reflect actual operation of the PCI Controller implemented on the IXP45X/IXP46X network processors.
Page 521: Pci Controller Functioning As Bus Target
For target-read transactions, a retry will be issued upon the receipt of a request to transfer data. Between the time that the retry occurs and the access to the IXP45X/ IXP46X network processors reoccurs, the PCI Controller retrieves the data from the previously requested location.
Page 522: Functional Description
An example of using the PCI Door Bell (PCI_PCIDOORBELL) is as follows: 1. The Intel XScale processor writes logic 1 to a bit or pattern of bits in the PCI Door Bell Register (PCI_PCIDOORBELL) to generate an interrupt on the PCI bus using PCI_INTA_N.
Page 523: Pci Target Interface Supported Commands
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.3.2.1 PCI Target Interface The PCI Target Interface provides read/write access to AHB agents, PCI Controller PCI Configuration registers (through Configuration cycles), and some PCI Controller CSRs.
Page 524: Pci Initiator Interface
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.3.2.1.2 PCI Bus Access to PCI Controller CSRs PCI Controller CSRs are accessed from PCI through read or write transactions whose address matches the PCI base address register pci_bar4. Pci_bar4 is written by the PCI Host during the bus configuration process to map the PCI Controller CSRs into the external PCI bus memory map.
Page 525: Pci Initiator Interface Supported Commands
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors This interface receives the address, word count, byte enables and PCI command type from the AHB side and performs the specified transaction on the PCI bus, handling all bus protocol and retry/disconnect situations.
Page 526: Pci Host Functions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.3.2.2.2 Initiator Read Transactions The PCI Master Interface receives read requests from the AHB Slave Interface or PCI- to-AHB DMA Controller via the Initiator Request FIFO. Read data is supplied to the AHB side using the Initiator Receive FIFO.
Page 527: Pci Controller Arbiter Configuration
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.3.2.3.1 PCI Arbiter The PCI Controller contains a PCI bus arbiter that supports four external masters in addition to the PCI Controller’s Initiator Interface. To enable the arbiter, the exp_pciarb pin must be a logic 1.
Page 528: Pci Clock And Reset Sourcing
Reset Source GPIO[13:0] GPIO[13:0] Both signals can be sourced from an external device as well. The Intel XScale processor can generate the PCI reset and PCI clock outputs to satisfy the reset timing requirements of the PCI bus. A PCI startup sequence could be as follows: 1.
Page 529: Pci Pad Drive Strength Compensation Support
PCI Controller to respond to PCI configuration cycles regardless of the state of Initialization Complete. When the Intel XScale processor is the PCI host performing system configuration, it is responsible for setting up the PCI Controller configuration registers as well as those of all the other devices on the bus.
Page 530: Ahb Master Interface
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.3.2.6.3 Effect on Internal PCI Arbiter If the internal PCI arbiter is enabled, a low level on exp_rcomp_complete will block all requests from external PCI masters and cause the arbiter to park the bus on the local PCI Initiator Interface.
Page 531: Pci-To-Ahb Address Translation
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Since the PCI controller performs pre-fetches when doing reads to the PCI_BAR0/1/2/3 address windows, the PCI_AHBMEMBASE must not be programmed to access any AHB I/O space or the AHB Queue Manager. To access AHB I/O space or the AHB Queue Manager, PCI_BAR5 must be used.
Page 532: Ahb Master Reads
8-bit fields in PCI_PCIMEMBASE is used. In this manner, the Intel XScale processor can map each range to any 16MB region in the full 4GB PCI address space by appropriately initializing the four base address fields in pci_pcimembase.
Page 533: Ahb-To-Pci Address Translation - Memory Cycles
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 92. AHB-to-PCI Address Translation – Memory Cycles AHB Address [25:24] pci_pcimembase Membase0 Membase1 Membase2 Membase3 register AHB Address [23:2] 24 23 PCI Address [31:0] to PCI Core B4293-01 10.3.2.10.2 AHB Slave Read Accesses...
Page 534 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller no request sent to the PCI Core. The Slave Interface only issues the retry on the cycle following the address phase on AHB, never in the middle of a burst. Bursts of 1 to 255 words are supported.
Page 535: Pci Byte Enable Generation
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 3. The hardware writes the data in PCI_CRP_WDATA to the enabled bytes in the addressed register of the PCI Core. During this operation, any access of CSR space from the AHB will be retried.
Page 536: Pci Controller Dma
For each direction, when a DMA channel is executing one transfer using the active DMA register set, the other DMA register set can be set-up by the Intel XScale processor to specify the next transfer. Both DMA channels can run concurrently so that individual PCI-to-AHB transfers and AHB-to-PCI transfers that make up the DMA transfers are interleaved on the AHB and PCI bus.
Page 537 Access to CSRs from the AHB bus is unrestricted while the DMA channels are operating. ability to access the PCI Controller Control and Status Registers is provided to allow the Intel XScale processor to set up the off-line DMA Register set while the on-line DMA Register set is operating.
Page 538: Ahb-To-Pci Dma-Transfer Byte Lane Swapping
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller DMA channel is disabled. The second register set may be active and using the DMA channel when the first DMA has finished. • One bit to define the byte order of the data transferred.
Page 539 ® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The DMA channels use 8-word burst accesses on the PCI and AHB busses (PCI-to-AHB and AHB -to-PCI) whenever possible. In the general case, a transfer will issue a starting burst from 1 to 7 words to align the AHB word address to an 8-word boundary.
Page 540: Ahb-To-Pci Dma Channel Operation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.3.3.1 AHB-to-PCI DMA Channel Operation The AHB-to-PCI (ATP) channel uses the PCI Core Initiator Request and Initiator Transmit FIFOs. The channel reads data from the AHB bus and writes it to a PCI target on word aligned boundaries.
Page 541: Data Byte Alignment And Addressing — Pci Endianness
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.3.4 Data Byte Alignment and Addressing — PCI Endianness The PCI Local Bus Specification, Rev. 2.2 defines the byte-addressing convention on the PCI Bus as little-endian. Since the byte addressing convention on the PCI bus is little-...
Page 542: Byte Lane Routing During Pci Target Accesses Of The Ahb Bus - Big-Endian Ahb Bus
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Figure 95. Byte Lane Routing During PCI Target Accesses of the AHB Bus – Big-Endian AHB Bus Write, Read, pci_csr.PDS = 1 pci_csr.PDS = 1 16 15...
Page 543: Byte Lane Routing During Pci Target Accesses Of The Ahb Bus - Little-Endian Ahb Bus
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 96. Byte Lane Routing During PCI Target Accesses of the AHB Bus – Little-Endian AHB Bus Write, Read, pci_csr.PDS = 1 pci_csr.PDS = 1 16 15...
Page 544: Byte Lane Routing During Ahb Slave Accesses Of The Pci Bus
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Figure 97. Byte Lane Routing During AHB Slave Accesses of the PCI Bus – Big-Endian AHB Bus Write, Read, pci_csr.ADS = 1 pci_csr.ADS = 1 16 15...
Page 545: Byte Lane Routing During Ahb Slave Accesses Of The Pci Bus
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 98. Byte Lane Routing During AHB Slave Accesses of the PCI Bus – Little-Endian AHB Bus Write, Read, pci_csr.ADS = 1 pci_csr.ADS = 1 16 15...
Page 546: Byte Lane Routing During Dma Transfers
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Figure 99. Byte Lane Routing During DMA Transfers AHB-to-PCI DMA, PCI-to-AHB DMA, DS = 1 DS = 1 16 15 16 15 PCI Data PCI Data 24 23...
Page 547: Pci Controller Interrupts
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 100. Byte Lane Routing During CSR Accesses PCI CSR Read PCI CSR Write 16 15 16 15 PCI Data PCI Data 24 23 16 15 24 23...
Page 548: Internal Interrupt Generation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller The PCI interrupt is enabled by the PDB bit of the Interrupt Enable Register (pci_inten). When this bit is set and at least 1 bit is set in the pci_pcidoorbell register, an interrupt is asserted on the PCI_INTA_N open-drain output.
Page 549: Pci Rcomp Circuitry
They are accessible from the PCI bus using configuration read and write transactions and from the Intel XScale processor by accessing the PCI Controller CSR-based PCI Configuration register port.
Page 550: Pci Configuration Register Descriptions
Reset Bits Name Description Value Access Access 31:1 Unique device identifier assigned by Intel. The state of the tlu_pci_id_sel DeviceID 0x8501 input determines which device Id is used. 15:0 VendorID Unique vendor identifier assigned to Intel by PCISIG 0x8086 ®...
Page 551: Status Register/Control Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.2.2 Status Register/Control Register pci_srcr Register Name: Block 0xC00000 0x04 0x02a00000 Offset Address Reset Value Base Address: Contains the Command and Status registers as specified in the PCI...
Page 552: Class Code/Revision Id Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_srcr (Sheet 2 of 2) Reset Bits Name Description Value Access Access Memory Write and Invalidate Enable. When set to a one, enables this MWIE device to generate the memory write and invalidate command.
Page 553: Bist/Header Type/Latency Timer/Cache Line Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.2.4 BIST/Header Type/Latency Timer/Cache Line Register pci_bhlc Register Name: Block 0xC00000 0x0c 0x00000000 Offset Address Reset Value Base Address: Provides BIST, Header Type, Latency Timer, and Cache Line Size...
Page 554: Base Address 1 Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_bar0 (Sheet 2 of 2) Reset Bits Name Description Value Access Access PREF Prefetchable memory indicator. Type Relocatable anywhere in 32-bit address space. Memory space indicator. Hard-wire to 0 for memory space.
Page 555: Base Address 3 Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register pci_bar2 Reset Bits Name Description Value Access Access 31:2 RWBase Read/Write bits of Base Address register. 0x00 Read-only bits of Base Address register. Specifies fixed 16MB address...
Page 556: Base Address 5 Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_bar4 Reset Bits Name Description Value Access Access 31:2 RWBase Read/Write bits of Base Address register. 0x00 Read-only bits of Base Address register. Specifies fixed 16MB address...
Page 557: Max_Lat, Min_Gnt, Interrupt Pin, And Interrupt Line Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register pci_sidsvid Reset Bits Name Description Value Access Access 31:1 SDeviceID Subsytem Device ID 0x0000 15:0 SVendorID Subsystem Vendor ID 0x0000 10.5.2.12 Max_Lat, Min_gnt, Interrupt Pin, and Interrupt Line Register...
Page 558: Csr Address Map
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_rtotto Reset Bits Name Description Value Access Access 31:1 reserved Reserved 0x00 Specifies value for the Retry timer. Specifies the maximum number of retries the Master Interface will accept before terminating the transaction.
Page 559: Pci Controller Non-Prefetch Address Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 201. CSR Address Map (Sheet 2 of 2) Register Name Description Reset Value Page Offset Offset 0x4c 0x4c pci_atpdma1_ahbaddr AHB-to-PCI DMA AHB Address Register 1 0x00000000...
Page 560: Pci Controller Non-Prefetch Write Data Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_np_cbe Reset Bits Name Description Value Access Access 0x0000 31:8 reserved reserved – read as 0 none Byte enables driven onto the PCI_CBE_N[3:0] lines of the PCI bus during...
Page 561: Pci Controller Configuration Port Address/Command/Byte
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.3.5 PCI Controller Configuration Port Address/Command/Byte Enables Register pci_crp_ad_cbe Register Name: Block 0xC00000 0x10 0x00000000 Offset Address Reset Value Base Address: PCI configuration port address/command/byte enables register.
Page 562: Pci Controller Configuration Port Write Data Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.5.3.6 PCI Controller Configuration Port Write Data Register pci_crp_wdata Register Name: Block 0xC00000 0x14 0x00000000 Offset Address Reset Value Base Address: PCI configuration port write data register. Provides write data for CSR-initiated accesses of the PCI Controller PCI configuration registers in the PCI Core.
Page 563: Pci Controller Control And Status Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.3.8 PCI Controller Control and Status Register pci_csr Register Name: Block 0xC00000 0x1c 0x0000000x Offset Address Reset Value Base Address: Control and status for the PCI Controller.
Page 564: Pci Controller Interrupt Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.5.3.9 PCI Controller Interrupt Status Register pci_isr Register Name: Block 0xC00000 0x20 0x00000000 Offset Address Reset Value Base Address: Indicates the PCI controller interrupt source(s). Register Description: Access: (See below.)
Page 565: Dma Control Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.3.10 PCI Controller Interrupt Enable Register pci_inten Register Name: Block 0xC00000 0x24 0x00000000 Offset Address Reset Value Base Address: Interrupt enables for the interrupt status bits in the pci_isr register.
Page 566: Ahb Memory Base Address Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_dmactrl Reset Bits Name Description Value Access Access 31:1 reserved reserved – read as 0 0x0000 PCI-to-AHB DMA error for buffer 1. Set to a 1 when the DMA transfer PADE1 specified by the pci_ptadma1_xxx registers terminates due to an error.
Page 567: Ahb I/O Base Address Register
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register pci_ahbmembase Reset Bits Name Description Value Access Access 31:2 Upper 8 AHB address bits for PCI accesses that target pci_bar0. By default AHBbase0 0xc0 this register maps to an upper region of the AHB memory map.
Page 568: Ahb Doorbell Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller Register pci_pcimembase Reset Bits Name Description Value Access Access 31:2 Upper 8 PCI address bits for AHB accesses that target the first 16MB PCI PCIbase0 0x00 memory partition.
Page 569: Pci Doorbell Register
Offset Address Reset Value Base Address: The Intel XScale processor writes this register to generate an interrupt to an external PCI device on PCI_INTA_N. Any bit set to a 1 will generate the PCI interrupt if the PCI doorbell interrupt is enabled (pci_inten.PDBEN = 1).
Page 570 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.5.3.18 AHB-to-PCI DMA PCI Address Register 0 pci_atpdma0_pciaddr Register Name: Block 0xC00000 0x44 0x00000000 Offset Address Reset Value Base Address: Destination address on the PCI bus for AHB-to-PCI DMA transfers.
Page 571: Ahb-To-Pci Dma Ahb Address Register 1
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.3.20 AHB-to-PCI DMA AHB Address Register 1 pci_atpdma1_ahbaddr Register Name: Block 0xC00000 0x4c 0x00000000 Offset Address Reset Value Base Address: Source address on the AHB bus for AHB-to-PCI DMA transfers.
Page 572 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.5.3.22 AHB-to-PCI DMA Length Register 1 pci_atpdma1_length Register Name: Block 0xC00000 0x54 0x00000000 Offset Address Reset Value Base Address: Provides word count and control for AHB-to-PCI DMA transfers.
Page 573: Pci-To-Ahb Dma Pci Address Register 0
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.5.3.24 PCI-to-AHB DMA PCI Address Register 0 pci_ptadma0_pciaddr Register Name: Block 0xC00000 0x5c 0x00000000 Offset Address Reset Value Base Address: Source address on the PCI bus for PCI-to-AHB DMA transfers.
Page 574 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.5.3.26 PCI-to-AHB DMA AHB Address Register 1 pci_ptadma1_ahbaddr Register Name: Block 0xC00000 0x64 0x00000000 Offset Address Reset Value Base Address: Destination address on the AHB bus for PCI-to-AHB DMA transfers.
Page 575: Pci-To-Ahb Dma Length Register 1
Initiator then terminates the cycle with a Target Abort response. With the ECC/ parity implementation of the DDRI and Expansion bus controller on the IXP45X/ IXP46X network processors, if an ECC or parity error exists on any word within an 8-word line (even if the PCI Initiator does not ask for this word), the PCI will respond with Target Abort on the first word of the read transfer.
Page 576 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.6.1.0.2 A PCI Target Read Received an Error Response During the AHB Read Operation After the PCI Transfer is Complete This scenario is possible since the AHB Master Interface does not know ahead of time how much data the PCI Initiator will need and thus keeps generating AHB read cycles until the Target Interface detects the end of the PCI read cycle.
Page 577: Error Handling As A Pci Initiator During Pci Direct Access From The Ahb Bus
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.6.2 Error Handling as a PCI Initiator During PCI Direct Access from the AHB Bus This section describes error handling procedures when the PCI Initiator Interface encounters a fatal error condition during a PCI transfer request received from the AHB Target Interface.
Page 578: Error Handling As A Pci Initiator During Non-Prefetch Operations
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller 10.6.3 Error Handling as a PCI Initiator During Non-Prefetch Operations This section describes error handling procedures when the PCI Initiator Interface encounters a fatal error condition during a PCI transfer request initiated by a non- prefetch operation.
Page 579: Error Handling During Ahb-To-Pci Dma Channel Operations
® ® PCI Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 10.6.5 Error Handling During AHB-to-PCI DMA Channel Operations 10.6.5.0.1 A PCI Write Received a Master Abort, Target Abort, PCI_TRDY_N Timeout, or RETRY Timeout During the DMA Transfer 1.
Page 580 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—PCI Controller ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Develepor’s Manual August 2006 Order Number: 306262-004US...
Page 581: Memory Controller
• Between 32 Mbytes and 1 Gbytes of 32-bit DDRI SDRAM for low cost solutions. • Two AHB ports for access from units other than Intel XScale processor (no critical word first support). • All MMR accesses must go through the South AHB port.
Page 582: Functional Blocks
DDRI SDRAM memory subsystem. 11.2.1 Functional Blocks The following needs to be considered when creating low level software for the IXP45X/ IXP46X network processors. The Memory Controller Unit (MCU) is made up of 3 parts (see Figure 101).
Page 583 DDR memory location that the Intel XScale processor is writing to. 1. Intel XScale processor needs to perform a read before it tries to write to the same exact DDR memory location. As stated above the MCU core will ensure any writes in the MAB or BIU will be processed before the read is returned thus ensuring the newest data is in DDR.
Page 584: Memory Controller Block Diagram
Core Processor Port (From BIU) The Core Processor Port provides a direct connection between the core bus interface of the IXP45X/IXP46X network processors and the Memory Controller. This Core Processor Port allows core transactions targeting the DDRI SDRAM to pass directly to the DDRI SDRAM.
Page 585: Address Decode Blocks
DDRI SDRAM from the Internal AHB Buses. All peripheral unit transactions targeting the DDRI SDRAM are claimed by these ports. Also all accesses to MMR space will be through the south AHB Internal bus port, this includes Intel XScale processor MMR accesses.
Page 586: Configuration Registers
DRAM. This enables the queuing of outstanding read transactions without modifying the existing peripheral units of the IXP45X/IXP46X network processors. Internal Bus Write Transactions will be posted to improve bus bandwidth.
Page 587: Ddri Sdram Memory Support
11.2.2 DDRI SDRAM Memory Support The memory controller for the IXP45X/IXP46X network processors supports one or two banks of DDRI SDRAM. DDRI SDRAM allows zero data-to-data wait-state operation. DDRI SDRAM offers an extremely wide range of configuration options emerging from the SDRAMs internal interleaving and bursting capabilities.
Page 588: Ddri Sdram Memory Configuration Options
1066 Mbyte/s 32 bit 1066 Mbyte/s Note: Based on DDRI 266 MHz SDRAM Figure 102 illustrates how two banks of DDRI SDRAM would interface with the IXP45X/ IXP46X network processors through the MCU. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual...
Page 589: Dual-Bank Ddri Sdram Memory Subsystem
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 102. Dual-Bank DDRI SDRAM Memory Subsystem DDR DIMM Using Network 128/256/512 Mbit, 1 Gbit Processor Devices DQS[4:0] DQS[4:0] Bank 0 DQ[31:0] DQ[31:0] CB[7:0] CB[7:0] RAS_N RAS_N...
Page 590: Supported Ddri Sdram Configurations
ECC and using x16 devices for the 32 bit DDRI data bus must also use a x16 device for the 8 bit ECC bus, even though 8 bits go unused. Note: For IXP45X/IXP46X network processors, the DDRI SDRAM 32-Bit Size Register (S32SR) will not be used, since it will always be in 32-bit mode. ®...
Page 591: Ddri Sdram Address Register Summary
DDRI SDRAM memory space must be aligned to a 32-Mbyte boundary and must never cross a 2-Gbyte boundary. Note: With 32-bit DDRI SDRAM attached to the IXP45X/IXP46X network processors, all DDRI SDRAM memory space behaves as 32-bit DDRI SDRAM and the value in S32SR is ignored.
Page 592: Programming Values For The Ddri Sdram 32-Bit Size Register (S32Sr[29:20])
010H (reserved) all other values Note: For the IXP45X/IXP46X network processors, this is always programmed to 0. Register. Example 21. Address Register Programming Example (Default Mode for IXP45X/IXP46X network processors) The user wants to program the DDRI SDRAM memory space to begin at 0000 0000H.
Page 593: Ddri Sdram Address Translation For 128/512 Mbit (X16/X8), 1 Gbitx8
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors • Perform DDRI initialization sequence using DDRI SDRAM Initialization Register SDIR register. • Refresh Frequency Register RFR - Program per JEDEC Spec using MCU clock of 133MHz Note: All other registers can use their default register values for operation.
Page 594: Bit To 32-Bit Addressing
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller Table 210. DDRI SDRAM Address Translation for 1 Gbitx16 Devices DDRI_MA [13:0] Column Notes: A10 is used for precharge variations on the read or write command. See Table 211 for more details.
Page 595: Page Hit/Miss Determination
DDRI_MA[13:0]. Therefore, the column address becomes four for the first write transaction. The MCU for the IXP45X/IXP46X network processors only supports a 32-bit data bus, although future products may support a 64-bit data bus width. The data bus width is selected by bit 2 of the SDCR (see “DDRI SDRAM Control Register 0 SDCR0”...
Page 596: Page Hit/Miss Logic For 128/256/512/1, 024-Bit Mode
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller If the current transaction hits the open page, then the page is already active and the read or write command may be issued without a row-activate command. When the next...
Page 597: Logical Memory Image Of A Ddri Sdram Memory Subsystem
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 105. Logical Memory Image of a DDRI SDRAM Memory Subsystem Page Address Registers Page 0 (closed) Page 1 (closed) Page 2 Bank0 Leaf0 Page 2 (OPEN)
Page 598: Ddri Sdram Commands
Interrupt a read or write burst. 1. This table copied from New DRAM Technologies by Steven Przybylski. 2. Shaded boxes indicate commands not supported by IXP45X/IXP46X network processors. They are included for completeness. 3. During a Mode Register Set command, DDRI_BA[1:0] = 00...
Page 599: Supported Ddri Sdram Extended Mode Register Settings
SDIR. The MCU supports the following DDRI SDRAM mode parameters: a. DLL = Enable/Disable b. Additive Latency (AL) is always zero for the IXP45X/IXP46X network processors. The MCU only supports an AL of zero because the MCU does not support back-to-back Active to Read or Write commands that would otherwise be in violation of tRCD (Active to Read/Write command delay): tRCD is obeyed at all times.
Page 600: Supported Ddri Sdram Mode Register Settings
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller Figure 107. Supported DDRII SDRAM Extended Mode Register Settings OCD is programmed DLL Enable: The DDR SDRAM Extended through the DDR 0: Enable Mode Register resides in the...
Page 601: Ddri Sdram Initialization Sequence (Controlled With Software)
B2452-02 If the DDRI SDRAM subsystem implements ECC (see Section 11.2.3, “Error Correction Detection”), then initialization software must initialize the entire memory array with the IXP45X/IXP46X network processors. It is important that every memory ® ® Intel IXP45X and Intel...
Page 602: Ddri Sdram Mode Programming
IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller location has a valid ECC byte. The Intel XScale processor processor must be used to fill the memory array with a constant, thereby initializing the associated ECC bytes in the process.
Page 603: Mcu Active, Precharge, Refresh Command Timing Diagram
Both parameters take into account CAS latency (JEDEC: t ) and Burst Length (JEDEC: BL). Note: Burst Length is fixed at four for the IXP45X/IXP46X network processors. Note: The MCU allows for back-to-back reads, so long as they are to a currently open page. ®...
Page 604: Mcu Ddr Read Command To Next Command Timing Diagram
Write Recovery (JEDEC: t ) and Write to Read (JEDEC: t Note: Burst Length is fixed at four for the IXP45X/IXP46X network processors. Note: The MCU allows for back-to-back Writes, so long as they are to an open page.
Page 605: Mcu Ddr Write Command To Next Command Timing Diagrams
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 112. MCU DDR Write Command to Next Command Timing Diagrams Next allowed Read: reg, BL=4. m_clk WTRD Next allowed Non-Read Command: reg, BL=4. WTCMD non-reg, BL=4, CAS=X...
Page 606: Ddri Sdram Pipelined Reads
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller 11.2.2.10 DDRI SDRAM Read Cycle The MCU performance is optimized for page hits and the MCUs behavior is different for the hit and miss scenario. The waveform for a read including the row activation in the case of a page miss is...
Page 607: Ddri Sdram Read, 36 Bytes, Ecc Enabled, Bl=4
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 114. DDRI SDRAM Read, 36 Bytes, ECC Enabled, BL=4 CK_N Valid Command Read A0-A9, COL n A11, A12 All Banks DIS AP One Bank BA0, BA1...
Page 608 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller A read that misses the open pages encounters a miss penalty because the currently open page needs to be closed before the read can be issued to the new page. Refer to Section 11.2.2.6, “Page Hit/Miss Determination”...
Page 609: Ddri Sdram Write Cycle
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.2.2.11 DDRI SDRAM Write Cycle All write transactions to the DDRI SDRAM are posted to the MCU in the memory transaction queues. This implies that the transaction completes between a given port and corresponding unit prior to data being written to the SDRAM array.
Page 610: Ddri Sdram Write, 36 Bytes, Ecc Enabled, Bl=4
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller Figure 115. DDRI SDRAM Write, 36 Bytes, ECC Enabled, BL=4 CK_N Valid Command Write A0-A9, Col n A11, A12 All Banks DIS AP One Bank BA0, BA1...
Page 611 ® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 1. Each of the MCU inbound memory transaction ports decodes the address to determine if the transaction should be claimed. — If the address falls in the DDRI SDRAM address range indicated by the SDBR, SBR0, SBR1, and S32SR the MCU claims the transaction and latches the transaction in the respective memory transaction queue.
Page 612: Ddri Sdram Pipelined Writes
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller Figure 116. DDRI SDRAM Pipelined Writes CK_N Command Write Write Write Write Write Bank Bank Bank Bank Bank Address Col b Col x Col n Col a...
Page 613: Refresh While The Memory Bus Is Not Busy
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 117. Refresh While the Memory Bus is Not Busy CK_N Valid Valid Command A0-A8 A9, A11, A12 All Banks One Bank BA0, BA1 Bank(s) Notes: PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address; AR = Autorefresh NOP commands are shown for ease of illustration;...
Page 614: Typical Refresh Frequency Register Values
For the IXP45X/IXP46X network processors, scrubbing is handled by software. If error reporting is enabled, the MCU logs the error type in ELOG0 or ELOG1 and the address in ECAR0 or ECAR1 when an error occurs.
Page 615: Ecc Write Flow
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.2.3.1 ECC Generation For write operations, the MCU generates the error correction code which is written along with the data. This section describes the operation of the DDRI SDRAM Control Block for ECC generation in a 64-bit wide memory and 64-bit region.
Page 616 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller The G-Matrix in Figure 119 generates the ECC. The data to be written is input to the matrix and the output is the ECC code. Each row of the G-Matrix indicates which data bits of DATA[63:0] needs to be XORed together to form the ECC bit.
Page 617: Ixp45X/Ixp46X Product Line G-Matrix (Generates The Ecc)
® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.2.3.2 ECC Generation for Partial Writes Figure 119. IXP45X/IXP46X product line G-Matrix (Generates the ECC) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual...
Page 618 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller If the memory transaction writes less than the data bus width programmed in the SDCR, then the DDRI SDRAM Control Block translates the write transaction into a read- modify-write transaction.
Page 619: Sub 64-Bit Ddri Sdram Write
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 120. Sub 64-bit DDRI SDRAM Write (D CK_N Command Read Write A0-A9, COL n COL n A11, A12 DIS AP DIS AP BA0, BA1 BA x...
Page 620: Ecc Checking
The ECC algorithm for a read transaction is: Read 64/32-bit data and 8-bit ECC (For the IXP45X/IXP46X network processors,32 bit read data is zero extended to 64 bits) Compute the syndrome by passing the 64-bit data through the G-Matrix and XORing the 8-bit result with the 8-bit ECC if the syndrome <>...
Page 621: Ecc Read Data Flow
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 121. ECC Read Data Flow Main Memory Memory 32-bit Zero-extend (0x00000000) Calculate ECC with G-matrix Calculate Syndrome by Comparing ECC w/Check Bits Data Corrector H-matrix Error Type/Location...
Page 622: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 623 ® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® ® Figure 122. Intel IXP45X and Intel IXP46X Product Line of Network Processors H- Matrix (Indicates the Single-Bit Error Location) ® ® Intel IXP45X and Intel...
Page 624 MCU detects an error during a read, the MCU logs the address where the error occurred and interrupts the Intel XScale processor. The Intel XScale processor decides how to fix the error through an interrupt handler. Software could decide to perform the scrubbing •...
Page 625: Ecc Disabled
Assume that bit 17 was corrupted in the array. Therefore, the bit has been inverted from 0 to 1. At some later point in time, the core wishes to read from the same address. The Intel XScale processor issues a read transaction which is latched by the CMTQ after the Core Address Decoder decodes the address and determines the read targets the DDRI SDRAM address space.
Page 626: Overlapping Memory Regions
• AHB bus Read latency (from request to valid data back for each of the AHB bus ports). • Core memory bus read latency (from the Intel XScale processor to DDRI request to valid data back for each of the eight outstanding read requests possible from the Intel XScale processor to memory.
Page 627: Mcu Error Response
IXP45X and Intel IXP46X Product Line of Network Processors 11.3 Power Failure Mode This mode is not supported by the IXP45X/IXP46X network processors as there is no support for self-refresh. 11.4 Interrupts/Error Conditions The MCU has two conditions which require intervention from the Intel XScale processor.
Page 628: Single-Bit Error Detection
• The MCU loads ELOG0[7:0] with the syndrome that indicated the error. • The MCU loads ECAR0[31:2] with the address where the error occurred. • Since the Intel XScale processor needs to scrub the error in the array, the MCU sets MCISR[0] to 1 (assuming it is not already set).
Page 629: Multi-Bit Error Detection
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.4.2 Multi-Bit Error Detection If a multi-bit error occurs during a read or write transaction and error reporting is enabled, the MCU sets MCISR[0] or MCISR[1] which asserts an interrupt to the core.
Page 630: Memory Controller Register Table
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller 11.6 Register Definitions A series of configuration registers control the MCU. Software can determine the status of the MCU by reading the status registers. Table 216 summarizes all of the MCU registers and provides links to register details.
Page 631 ® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 216. Memory Controller Register Table (Sheet 2 of 2) Page Address Register Name Description Reset Value with Details MCU Preemption Control Register - CC00 E540H MCU Preemption Control Register...
Page 632: Ddri Sdram Initialization Register Sdir
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller 11.6.1 DDRI SDRAM Initialization Register SDIR The DDRI SDRAM Initialization Register (SDIR) is responsible for programming the operation of the DDRI SDRAM device state machines. The SDIR provides a method for software to execute the DDRI SDRAM initialization sequence (see “DDRI SDRAM...
Page 633: Ddri Sdram Control Register 0 Sdcr0
DDRI SDRAM state machine are set in SDCR1. Note: Each parameter field contains either an IXP45X/IXP46X network processors-required value limit or an example value derived from a typical device datasheet. DDRI SDRAM Control Register 0 - SDCR0...
Page 634 19:1 (Reserved) 17:1 EDP: Data Path Latency in MCLK periods. A value of 10 should be programmed for the IXP45X/IXP46X network processors. 15:1 (Reserved) 13:1 WDL: Write Data Latency in MCLK periods. A value of 00 must be programmed for the IXP45X/IXP46X network processors.
Page 635: Ddri Sdram Control Register 1 Sdcr1
DDRI SDRAM state machine not specified in SDCR0. Note: Each parameter field contains either an IXP45X/IXP46X network processors-required value limit or an example value derived from a typical device datasheet. DDRI SDRAM Control Register 1 - SDCR1...
Page 636 NOTE: The MCU allows for back-to-back reads, so long as they are to open pages. RESERVED. A value of 0 must be used for the IXP45X/IXP46X (Reserved) network processors. 18:1 (Reserved) RFC: Auto Refresh Command Period in MCLK periods. This value is...
Page 637: Ddri Sdram Base Register Sdbr
Note: DDRI SDRAM memory space must never cross a 2 Gbyte boundary. Note: This register should be read back after being written, before the Intel XScale processor performs transactions which address the DDRI SDRAM. SDRAM Base Register - SDBR Register Name:...
Page 638: Ddri Sdram Boundary Register 0 Sbr0
Note: DDRI SDRAM memory space must never cross a 2-Gbyte boundary. Note: This register should be read back after being written, before the Intel XScale processor performs transactions which address the DDRI SDRAM. SDRAM Boundary Register 0 - SBR0 Register Name:...
Page 639: Ddri Sdram Boundary Register 1 Sbr1
Note: DDRI SDRAM Memory Space must never cross a 2-Gbyte boundary. Note: This register should be read back after being written, before the Intel XScale processor performs transactions which address the DDRI SDRAM. SDRAM Boundary Register - SBR1 Register Name:...
Page 640: Ecc Control Register Eccr
64-bit writes. See “ECC Disabled” on page 625. 0 = ECC Disabled (mode for Intel XScale processor ECC scrub) 1 = ECC Enabled (normal operation) Single Bit Error Correction Enable: Enables or disables the correction of a single bit error.
Page 641: Ecc Log Registers Elog0, Elog1
23:1 All Other Codes Are Reserved Note: Intel XScale processor BIU is logged for core transactions directed to the MCU via the Core MCU port only. Core transactions directed to the MCU via the IB port of the BIU will be logged as the IB BUS.
Page 642: Ecc Address Registers Ecar0, Ecar1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller 11.6.9 ECC Address Registers ECAR0, ECAR1 These registers are responsible for logging the addresses where the errors were detected on the local memory bus. Two errors can be detected and logged. The software knows which DDRI SDRAM address had the error by reading these registers and decoding the syndrome in the log registers.
Page 643: Ecc Test Register Ectst
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 11.6.10 ECC Test Register ECTST This register allows testing between the ECC logic and the memory subsystem (“ECC Testing” on page 625). To test error handling software, the programmer writes this register with a non-zero masking function.
Page 644: Memory Controller Interrupt Status Register Mcisr
11.6.11 Memory Controller Interrupt Status Register MCISR Setting the MCISR asserts an interrupt to the core. Upon an interrupt, the Intel XScale processor polls the interrupt status register for each unit. The interrupt status register tells the core the reason for the interrupt. The MCU has three interrupt conditions: first ECC error (MCISR[0]), second ECC error (MCISR[1]), and more than two ECC errors (MCISR[2]).
Page 645: Mcu Port Transaction Count Register Mptcr
“MCU Preemption Control Register MPCR” on page 645 used to optimize the memory controller operation. Note: For the IXP45X/IXP46X network processors, this value MUST remain programmed to 11H in order to prevent unfair arbitration and indeterminate results. MCU Port Transaction Count Register - MPTCR Register Name:...
Page 646: Refresh Frequency Register Rfr
Medium priority level, the preemption control will work as expected. Note: Preemption is not supported on the IXP45X/IXP46X network processors, therefore this register must remain set at its default value. MCU Preemption Control Register - MPCR...
Page 647: Sdram Page Registers Sdpr0-7
® ® Memory Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register Refresh Frequency Register - RFR Bits Name Description Default Access 31:1 (Reserved) 00000H Refresh Interval: Programs the number of clocks that triggers a request for a refresh cycle on the DDRI SDRAM interface. If all zeroes, refresh cycles are disabled.
Page 648 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Memory Controller ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 649: Expansion Bus Controller
Interface (HPI) target devices. The Expansion bus controller also has an arbiter that supports up to four external devices that can master the Expansion bus. External masters can also access internal slaves such as the memory controller in the IXP45X/ IXP46X network processors.
Page 650: Outbound Transfers
Outbound Transfers For outbound data transfers, the Expansion bus controller occupies 256 Mbytes of address space in the memory map of the IXP45X/IXP46X network processors and contains a 1-deep address queue, an 8-word write data fifo, and an 8-word read data FIFO.
Page 651 For 16-bit Synchronous Intel devices, the burst length must be programmed to 16-word bursts. For 32-bit Synchronous Intel devices, the burst length must be programmed to 8-word bursts. The latency count must be programmed to the appropriate code that is defined in the Synchronous Intel StrataFlash Memory specification.
Page 652: Supported Ahb Commands
The EX_IOWAIT_N signal is available to be shared by the devices attached to chip 0 through 7, when the chip selects are configured in Intel or Motorola mode of operation. The EX_IOWAIT_N signal allows an external device to hold off completion of the read or write phase of a transaction until the external device is ready to complete the transaction.
Page 653: Trimmed Version Of Ixp45X/Ixp46X Network Processors Memory Map
0x00000000 in non-volatile storage on the Expansion Bus. The first instruction execution of the Intel XScale processor is located at address 0x00000000. Once the boot sequence starts, the Intel XScale processor will switch bit 31 of the Configuration Register 0 (EXP_CNFG0) from logic 1 to logic 0, at an appropriate time.
Page 654: Chip Select Address Allocation When There Are No 32-Mbyte Devices Programmed
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller Figure 124. Chip Select Address Allocation when there are no 32-MByte Devices Programmed base + 0xFFFFFFF CNFG[4:1] = 0b1111 SIZE = 16 MBytes MBytes cs_n[0] (alias)
Page 655: Chip Select Address Allocation When A 32-Mbyte Device Is Programmed
Four- and eight-word reads to Synchronous Intel only generate one burst access to the device. Byte enables are generated for both reads and writes and are valid the same cycles (T1-T4 phases) as EX_ADDR is valid.
Page 656: Expansion Bus Address And Data Byte Steering
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller Table 220. Expansion Bus Address and Data Byte Steering (Sheet 1 of 3) Device Width AHB Address Expansion Bus Connected to AHB Bus Value Address Value...
Page 657 ® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 220. Expansion Bus Address and Data Byte Steering (Sheet 2 of 3) Device Width AHB Address Expansion Bus Connected to AHB Bus Value Address Value...
Page 658: Expansion Bus Interface Configuration
When designing with the Expansion Bus Interface, placing the devices on the correct chip selects is required. Chip Select 0 through 7 can be configured to operate with devices that require an Intel, Synchronous Intel, Micron* ZBT or Motorola* Micro-Processor style bus accesses.
Page 659 EX_RDY_N[3:0]. The ready bit is only used when the mode of operation is set to Texas Instruments HPI mode. The ready bits are used to hold off the Intel XScale processor when the given DSP is not ready to complete the transfer.
Page 660 • T4 – Hold Timing • T5 – Recovery Phase For Synchronous Intel mode, the T1,T2, T3, T4, T5 timing parameters are only used for writes. For Synchronous Intel reads, the Expansion bus controller uses the Count value programmed in the EXP_SYNCINTEL_COUNT register to determine how many cycles before data is valid.
Page 661: Using I/O Wait
– Hold Timing parameter. In HPI mode of operation, the Hold Phase is defined the same as described for the Intel and Motorola modes of operation, but must be set to a minimum value of one additional cycle (T4 >= 0x1).
Page 662: I/O Wait Normal Phase Timing
Note: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last three clock cycles. The data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts EX_IOWAIT_N.
Page 663: I/O Wait Extended Phase Timing
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 128. I/O Wait Extended Phase Timing T1=3 h T2=3 h T3=F h T4=3 h T5=F h 4 Cycles 4 Cycles 16 Cycles 4 Cycles 16 Cycles ..
Page 664: Special Design Knowledge For Using Hpi Mode
If the Expansion Bus CS (Chip-Select) is configured to operate to operate in HPI-8 Mode, then a STRH (16-bit write) Intel XScale processor instruction must be used for writing to the HPI-8 device, even though it is in an 8-bit device. If a STRB (8-bit write) instruction is used instead, then the Intel XScale processor’s data abort handler will be...
Page 665: Expansion Bus Outbound Timing Diagrams
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 222. HPI HCNTL Control Signal Decoding hcntl[1:0] Required Access Read / write control register (HPIC) Read / write data register (HPID) HPI-8: Post-increment HPIA on reads, pre-increment on writes.
Page 666: Expansion Bus Write (Intel, Multiplexed Mode)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.1 Intel, Multiplexed-Mode Write Access Figure 129. Expansion Bus Write (Intel, Multiplexed Mode) 2-5 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles ALE Extended EX_CLK...
Page 667: Expansion Bus Read (Intel, Multiplexed Mode)
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.2 Intel, Multiplexed-Mode Read Access Figure 130. Expansion Bus Read (Intel, Multiplexed Mode) 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles 2-5 Cycles ALE Extended EX_CLK...
Page 668: Expansion Bus Write (Intel Simplex-Mode, Synchronous Intel)
Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.3 Intel Simplex-Mode and Synchronous Intel Write Access Figure 131. Expansion Bus Write (Intel Simplex-Mode, Synchronous Intel) 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles EX_CLK...
Page 669: Expansion Bus Read (Intel Simplex-Mode)
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.4 Intel Simplex-Mode Read Access Figure 132. Expansion Bus Read (Intel Simplex-Mode) 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles EX_CLK recov EX_CS_N[0] EX_ADDR[24:0]...
Page 670: Intel Synchronous 8-Word Read
IDLE B4400-01 The above timing diagram shows an 8-word read to a Synchronous Intel device such as Synchronous Intel StrataFlash. Depending on the EX_CLK period, the latency count bits in the Intel Synchronous Device read configuration register needs to be programmed appropriately.
Page 671: Intel Synchronous One-Word Read
Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.6 Synchronous Intel 1-Word Read Access Figure 134. Intel Synchronous One-Word Read - 0 - - 1 - - 3 - - 4 - - 5 - - 6 -...
Page 672: Micron* Zbt Write/Read/Write
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.7 Micron* ZBT Write/Read/Write Access Figure 135. Micron* ZBT Write/Read/Write - 0 - - 1 - - 3 - - 4 - - 5 - - 6 -...
Page 673: Micron* Zbt 8-Word Read
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.8 Micron* ZBT 8-Word Read Access Figure 136. Micron* ZBT 8-Word Read - 0 - - 1 - - 3 - - 4 - - 5 -...
Page 674: Micron* Zbt 4-Word Write
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.9 Micron* ZBT 4-Word Write Access Figure 137. Micron* ZBT 4-Word Write - 0 - - 1 - - 2 - - 3 - - 4 -...
Page 675: Expansion Bus Write (Motorola*, Multiplexed Mode)
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.10 Motorola*, Multiplexed-Mode Write Access Figure 138. Expansion Bus Write (Motorola*, Multiplexed Mode) 2-5 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles ALE Extended EX_CLK...
Page 676: Expansion Bus Read (Motorola*, Multiplexed Mode)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.11 Motorola*, Multiplexed-Mode Read Access Figure 139. Expansion Bus Read (Motorola*, Multiplexed Mode) 2-5 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles ALE Extended EX_CLK...
Page 677: Expansion Bus Write (Motorola*, Simplex Mode)
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.12 Motorola*, Simplex-Mode Write Access Figure 140. Expansion Bus Write (Motorola*, Simplex Mode) 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles EX_CLK recov EX_CS_N[0]...
Page 678: Expansion Bus Read (Motorola*, Simplex Mode)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.13 Motorola*, Simplex-Mode Read Access Figure 141. Expansion Bus Read (Motorola*, Simplex Mode) 1-4 Cycles 1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles EX_CLK recov EX_CS_N[0]...
Page 679: Expansion Bus Write (Ti* Hpi-8 Mode)
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.1.8.14 TI* HPI-8 Write Access Figure 142. Expansion Bus Write (TI* HPI-8 Mode) 3-4 Cycles 3-4 Cycles 2-16 Cycles 3-4 Cycles 2-17 Cycles EX_CLK recov EX_CS_N[0]...
Page 680: Expansion Bus Write (Ti* Hpi-16, Multiplexed Mode)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.1.8.16 TI* HPI-16, Multiplexed-Mode Write Access Figure 144. Expansion Bus Write (TI* HPI-16, Multiplexed Mode) 3-4 Cycles 3-4 Cycles 2-16 Cycles 3-4 Cycles 2-17 Cycles EX_CLK...
Page 681: Expansion Bus Write (Ti* Hpi-16, Simplex Mode)
B3756-001 12.4.2 Inbound Transfers Inbound transfers are initiated by external masters and target IXP45X/IXP46X network processors when EX_SLAVE_CS_N is asserted. The Expansion bus controller should ignore all control signals when EX_SLAVE_CS_N is not asserted and never drive EX_WAIT_N/EX_DATA/EX_PARITY when its not being accessed. External masters must request the Expansion bus and only own the bus when it is granted.
Page 682: Supported Inbound Expansion Bus Transfers
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller and 8-word aligned read transfers for 8-word burst lengths. The Expansion bus controller also supports write data transfers for byte, halfword (half-word aligned), 1- word (word aligned), and 8-word (8-word aligned) burst lengths. The Expansion bus...
Page 683 ® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors EX_SLAVE_CS_N but deasserting EX_RD_N for at least one cycle. The new transfer starts when EX_RD_N is asserted and the Expansion bus controller will always assert EX_WAIT_N one cycle later.
Page 684 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller EX_SLAVE_CS_N or EX_WR_N. The master must transfer all 8-words during an 8-word write burst. The master can also choose to do back-to-back 8-word writes by leaving EX_SLAVE_CS_N asserted but deasserting EX_WR_N for at least one cycle.
Page 685: Expansion Bus Inbound State Diagram
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 148. Expansion Bus Inbound State Diagram EX_IXPCS_N = ‘0’ and (EX_WR_N = ‘0’ or EX_RD_N = ‘0’) and not WAIT EX_IXPCS_N = ‘1’ IDLE DATA All States EX_IXPCS_N = ‘0’...
Page 686 12.4.3 Arbitration The Expansion bus controller provides arbitration between IXP45X/IXP46X network processors and up to four external masters. An external arbiter can also be used, if desired. The external arbiter is enable by the EX_ADDR driving bit 6 of EX_ADDR to logic 0.
Page 687: Internal Arbitration
If they become indeterminate, excessive power consumption will occur in the PAD input buffers. When the IXP45X/IXP46X network processors are granted or parked on the Expansion bus, the processors will drive the shared Expansion bus signals to a de-asserted or stable state to minimize power consumption.
Page 688: External Arbiter
Multiple Processors Connected by the Expansion Bus When connecting multiple IXP45X/IXP46X network processors together via the Expansion bus, a special reset sequence is required to ensure that each of the IXP45X/ IXP46X network processors has independent configuration values as defined in “Configuration Register 0”...
Page 689: Multiple Ixp45X/Ixp46X Network Processors Connected Back-To-Back
If there are no other masters on the exp bus besides the two IXP45X/IXP46X network processors, it is not necessary to tie an address bit to ex_burst. In this case, ex_burst can be tied to vss.
Page 690: Expansion Bus Inbound Timing Diagrams
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.5 Expansion Bus Inbound Timing Diagrams The next several timing diagrams show several representations of some of the supported inbound bus protocol. The Expansion bus controller is not limited to the possibilities of the timing diagrams shown.
Page 691: Eight-Word Inbound Write
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 151. Back-to-Back 1-Word Writes without Deasserting EX_SLAVE_CS_N - 10 - 11 - 12 EX_CLK EX_IXPCS_N EX_ADDR ADDR0 ADDR1 ADDR2 EX_RD_N EX_WR_N EX_BE_N EX_BURST EX_WAIT_N EX_DATA...
Page 692: Eight-Word Inbound Write With Master Wait States
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller Figure 152. Eight-Word Inbound Write - 0 - - 1 - - 3 - - 4 - - 5 - - 6 - - 7 -...
Page 693: Eight-Word Inbound Write
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 153. Eight-Word Inbound Write - 0 - - 1 - - 2 - - 3 - - 4 - - 5 - - 6 -...
Page 694: Eight-Word Inbound Write With Ex_Slave_Cs_N Deassertion
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller decided to start another NOP cycle in cycle 3. If EX_WAIT_N was asserted in cycle 2, the external master cannot start a NOP in cycle 3. It must wait until EX_WAIT_N is sampled deasserted.
Page 695: Back-To-Back 1-Word Inbound Reads With Ex_Slave_Cs_N
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.5.7 Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N Figure 156. Back-to-Back 1-Word Inbound Reads with EX_SLAVE_CS_N - 0 - - 1 - - 2 - - 3 -...
Page 696: Back-To-Back 1-Word Reads Without Ex_Slave_Cs_N Deasserted
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.5.8 Back-to-Back 1-Word Reads without EX_SLAVE_CS_N Deasserted Figure 157. Back-to-Back 1-Word Reads without EX_SLAVE_CS_N Deasserted - 0 - - 1 - - 3 - - 4 -...
Page 697: Eight-Word Inbound Read With Master Wait States
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.4.5.10 Eight-Word Inbound Read with Master Wait States Figure 159. Eight-Word Inbound Read with Master Wait States - 0 - - 1 - - 3 -...
Page 698: Eight-Word Inbound Read With Deassertion Of Ex_Slave_Cs_N
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.4.5.11 Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N Figure 160. Eight-Word Inbound Read with Deassertion of EX_SLAVE_CS_N - 0 - - 1 - - 3 -...
Page 699: Arbitration When Grantremove Bit In Exp_Mst_Control Is Clear
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The above timing diagram shows the request and grant lines for two external masters. The Expansion bus controller owns the bus in cycles 0 and 1. The Expansion controller must tri-state the shared Expansion bus outputs on or before cycle 3.
Page 700: External Expansion Bus Timing Diagram
The Expansion bus controller contains configuration registers beyond what is required for its own configuration. There are several bits of configuration signals provided as output from the Expansion bus controller to the rest of the IXP45X/IXP46X network processors. These signals provide the AHB with functions like the software interrupt...
Page 701: Sampling Ex_Addr During Reset
The Expansion bus controller samples EX_ADDR when reset_early_n = ‘0’, which occurs during power up or during a watch dog reset. However, the Expansion bus controller only samples the Intel XScale processor Clock Set bits, EX_ADDR[23:21], when reset_early_n = ‘0’ and reset_cold_n = ‘0’.
Page 702: Register Legend
Specifies the parity error status. 0x00000000 Table This register is used to set the read latency count See Register 0xC4000124 EXP_SYNCINTEL_COUNT 0x00000000 when a Synchronous Intel Device is accessed. Table ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual...
Page 703: Timing And Control Registers For Chip Select 0
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.5.1 Timing and Control Registers for Chip Select 0 Register Name: EXP_TIMING_CS0 CS0: Hex Offset Address: 0XC4000000 Reset Hex Value: 0xBFFF3C4x Register Timing and Control Registers...
Page 704: Timing And Control Registers For Chip Select 3
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.5.4 Timing and Control Registers for Chip Select 3 EXP_TIMING_CS3 Register Name: CS3: 0XC400000C Hex Offset Address: Reset Hex Value: 0x00000000 Register Timing and Control Registers...
Page 705: Timing And Control Registers For Chip Select 6
1 = Chip Select x enabled 0 = Parity is not generated or compared 1 = Parity is generated and compared PAR_EN Parity is only supported for Intel, Motorola, and Micron ZBT modes. 00 = Generate normal address phase timing 29:28 T1 –...
Page 706: Configuration Register 0
Sync_Intel 0 = Target device is not a Synchronous Intel StrataFlash 1 = Target device is a Synchronous Intel StrataFlash 0 = Target device is not one of the IXP45X/IXP46X network processors EXP_CHIP 1 = Target device is one of the IXP45X/IXP46X network processors.
Page 707: Ex_Addr Operation
0 = Located at “50000000” (normal mode) 1 = Located at “00000000” (boot mode) 30:24 (Reserved) (Reserved) Allow a slower Intel XScale processor clock speed to override ® Intel XScale Processor EX_ADDR[23: device fuse settings. However cannot be used to over clock core 23:21 speed.
Page 708 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller Table 229. Configuration Register 0 Description (Sheet 2 of 2) Name Reset Value Description Controls the USB clock select 1 = USB Host/Device clock is generated internally 0 = USB Device clock is generated from GPIO[0].
Page 709: Processor Operation Speed
266 MHz 266 MHz Note that the Intel XScale processor can operate at slower speeds than the factory programmed speed setting. This is done by placing a value on Expansion bus address bits 23,22,21 when PLL_LOCK is deasserted and knowing the speed grade of the part from the factory.
Page 710: Expansion Bus Configuration Register 1-Bit Definition
When the bit is 1, the type of coherency depends on the P-attribute bit. The P-attribute bit is associated with each 1-Mbyte page. The P-attribute bit is output, from the Intel XScale processor, with any store or load access associated with that page.
Page 711 When the bit is 1, the type of coherency depends on the P-attribute bit. The P-attribute bit is associated with each 1-Mbyte page. The P-attribute bit is output, from the Intel XScale processor, with any store or load access associated with that page.
Page 712 When the bit is 1, the type of coherency depends on the P-attribute bit. The P-attribute bit is associated with each 1-Mbyte page. The P-attribute bit is output, from the Intel XScale processor, with any store or load access associated with that page.
Page 713: Exp_Unit_Fuse_Reset
® ® Expansion Bus Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 12.5.11 EXP_UNIT_FUSE_RESET EXP_UNIT_FUSE_RESET Register Name: 0xC4000028 0xXXXXXXXX Physical Address: Reset Hex Value: Specifies the value of the fuse register. Register Description: Access: See below. RESERVED Register...
Page 714 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller Register EXP_UNIT_FUSE_RESET Reset Bits Name Description Access Value NPE-C 0 = NPE-C Ethernet Enabled FUSE[18] ETHERNET 1 = NPE-C Ethernet Disabled 0 = NPE-B Ethernet 0 Enabled...
Page 715: Utopia/Ethernet Configuration Options
After being reset, the coprocessor interfaces will go back to the default reset mode for that interface. Additionally, the Intel XScale processor factory speed cannot be changed by software. Table 232.
Page 716: Exp_Smiidll
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller 12.5.12 EXP_SMIIDLL EXP_SMIIDLL Register Name: 0xC400002C 0x00000000 Physical Address: Reset Hex Value: DLL bits for SMII used by the SMII DLL. Register Description: Access: See below.
Page 717 This specifies if the Expansion bus arbiter should mask all external requests so that an external master cannot access the Expansion bus. This is necessary to allow IXP45X/IXP46X network processors to perform atomic accesses to Expansion targets. This bit is only used ArbMask# when the Expansion bus arbiter is enabled.
Page 718 PCI traffic is desired, there are two methods to support this. 1. Program the PCI Controller to transfer the data to main memory and then use the Intel XScale processor to transfer the data from main memory to the Expansion bus.
Page 719: Ex_Addr Value To Access Exp_Inbound_Addr Register
2nd master will observe 0xFFFFFFFF, which means that the resource is locked and it does not have access to the resource. The IXP45X/IXP46X network processors do not have any hardware to prevent the 2nd master from accessing the locked resource and it is up to software to ensure that the 2nd master complies to this protocol.
Page 720: Exp_Lock1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Expansion Bus Controller The EXP_LOCK0 register can be read/written from the AHB bus and from an external master. External masters accesses to the EXP_LOCK0 register is only supported for word accesses.
Page 721: Exp_Parity_Status
The OR of InErrorSts and OutErrorSts is generated to form exp_parity_error which is routed to the Interrupt Controller which can generate interrupts to Intel XScale processor. In the event of multiple inbound parity errors or multiple outbound parity...
Page 722: Exp_Syncintel_Count
(i.e mov R4,R4). 12.5.18 EXP_SYNCINTEL_COUNT EXP_SYNCINTEL_COUNT Register Name: 0xC4000124 0x00000000 Physical Address: Reset Hex Value: This register is used to set the read latency count when a Synchronous Intel Device Register Description: is accessed. Access: See below. (Reserved) Count Register EXP_SYNCINTEL_COUNT Reset...
Page 723: Hss Coprocessor
IXP400 Software Programmer’s Guide and may be a subset of the features described below. The HSS coprocessor enables the IXP45X/IXP46X network processors to communicate in a Time Divisible Multiplexed (TDM) bit serial fashion with external chips. The HSS interfaces are six-wire, serial interfaces that can operate at speeds from 512 KHz to 8.192 MHz.
Page 724: High-Speed Serial Interface Receive Operation
• Voice • 56-K mode This characterization will be assigned on a time-slot basis using Intel-supplied APIs. For example, time slot 0 may be defined as a voice cell, time slot 1 as an HDLC wrapped packet, time slot 2 as an undefined time slot, and time slot 3 defined as an 56-K mode cell.
Page 725: High-Speed Serial Interface Transmit Operation
When the HSS transmit interface processes the third byte (time slot 2), the look-up table will indicate that the byte to be transmitted is an unassigned cell. Using Intel- supplied APIs, the Intel XScale processor can program the HSS interface to transmit one of three values in an unassigned time slot: •...
Page 726: Theory Of Operation
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor • Ten FIFOs per HSS core, 5 for TX, 5 for RX (1 voice, 4 HDLC). • The four HDLC FIFOs can be programmed to operate as either 2 FIFOs or 1 FIFO.
Page 727: Fifos And Lookup Tables
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors The number of timeslots expected by the HSS core is programmable by the NPE Core. The maximum frame size is 1024 bits, the maximum frame pulse offset is 1,023 bits.
Page 728: Look-Up Table Organization
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 165. Look-Up Table Organization Transmitted/received first Transmitted/received last E1/T1 Lookup table size is dependent on the protocol used dual MVIP quad MVIP Timeslot number 64-79 0-15...
Page 729: Hss Core Rx Buffer Structure (Identical To Tx Buffer Structure)
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors issue instructions as appropriate. As the HSS knows which core/buffer the NPE Core is going to service. The HSS will ensure that the FIFO related instructions will be directed towards the correct buffer.
Page 730: Endianness
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor 13.3.2 Endianness The endianness of the data bus must be taken into account when writing data to the HSS for transmitting. The same goes for reading back received data.
Page 731: Tx Frame Sync Example (Presuming Zero Offset)
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors The HSS will not request data from the NPE Core until it has synced up to the TX frame pulse. Meaning that the HSS must detect two consecutive frame pulses (in the case of gapped frame pulses, then sync is assumed on the detection of the second frame pulse).
Page 732: Frx Frame Sync Example (Presuming Zero Offset)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 169. FRX Frame Sync Example (Presuming Zero Offset) hss_rx_clock Correct interval hss_rx_frame data data data hss_rx_data Data from here is processed B4237-02 13.3.4 Underflow/Overflow/Unexpected Frame Pulse Underflow occurs if the HSS attempts to read from a FIFO which has not been filled by the NPE Core.
Page 733: Frameless Data Protocol Support
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors the error register, all FIFO errors and the FIFOs themselves in the HSS core for that direction are cleared. When the NPE Core reads the error register, the RX condition signals are cleared.
Page 734: Hss Registers And Clock Configuration
There is one register titled the HSS Clock Divider Register that provides a means to generate a unique data clock for each of the two HSS interfaces for the IXP45X/IXP46X network processors. The IxHssAcc API will configure the HSS clock divider register with the appropriate values depending on which clock frequencies is selected, being 512 KHz, 1.536 MHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, and 8.192 MHz.
Page 735: Overview Of Hss Clock Configuration
When the frequencies of 2.048, 4.096, or 8.192 MHz are used for T1, the data rate for each T1 remains at 1.544 MHz by making certain time slots within a frame unassigned and with no data. The HSS for the IXP45X/IXP46X network processors can be configured to discard unassigned time slots. Table 239.
Page 736: Jitter Definitions
HSS Supported Framing Protocols The following sections provide an overview of some Framing Protocols supported by each of the HSS interfaces for the IXP45X/IXP46X network processors, in addition to the recommended HSS interface setting for each protocol that are configured using the ®...
Page 737: T1 Tx Frame, Hss Generating Frame Pulse
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 170. T1 TX Frame, HSS Generating Frame Pulse hss_tx_clock hss_tx_frame _out_en hss_tx_frame_out hss_tx_data_out _en hss_tx_data_out FBit data1 data2 data 191 data 192 FBit data1 B4238-02 Figure 170 illustrates a typical T1 frame with active high frame sync (level) and a posedge clock for generating data.
Page 738: T1 Rx Frame Using External Frame Pulse
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 172, as stated in Section 13.3, “Theory of Operation” on page 726, the FBit to be received is padded with 7 other bits (zeros) and placed into the HSS Receive FIFO.
Page 739: E1 Tx Frame, Hss Generating Frame Pulse
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 173. E1 TX Frame, HSS Generating Frame Pulse hss_tx_clock hss_tx_frame _out_en hss_tx_frame_out hss_tx_data_out _en hss_tx_data_out data 1 data 2 data 3 data 255 data 256 data 1...
Page 740: E1 Rx Frame, Externally Generated Frame Pulse
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 175. E1 RX Frame, Externally Generated Frame Pulse hss_rx_clock hss_rx_frame data1 data2 data3 data255 data256 data1 data2 hss_rx_data B4246-02 By using the IxHssAcc API, the following settings should be considered when configuring HSS interface for E1 operation: •...
Page 741: Gci Frames, Internally Generated Frame Pulse (Line-Card Mode)
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors The HSS also supports GCI multiplexed mode, which means a number of GCI- compatible devices can be connected to the same serial bus, the numbers allowed are 1, 3, 4 and 8.
Page 742: Mvip
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 177. GCI Frames, Internally Generated Frame Pulse (Termination Mode) hss_tx_clock subframe 0 subframe 1 subframe 2 subframe 3 7 6 5 4 3 2 1 0...
Page 743: Mvip, Interleaved Mapping Of A T1 Frame To An E1 Frame
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors • Frame sync simultaneous with first data nibble – set TX frame offset and RX frame offset due to HSS logic, different values due to external device can be accommodated.
Page 744: Mvip, Frame Mapping A T1 Frame To An E1 Frame
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 178. MVIP, Interleaved Mapping of a T1 Frame to an E1 Frame Note: In timeslot 0, the frame timeslot is not ignored Every fourth timeslot received by the HSS is discarded, meaning it is not loaded into the FIFO and is therefore not sent to the NPE Core.
Page 745: Mvip, Byte Interlacing Two E1 Streams Onto A 4.096-Mbps Backplane
® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 180. MVIP, Byte Interlacing Two E1 Streams onto a 4.096-Mbps Backplane 4. 096 MHz clock Frame pulse Bits Timeslots 10a 10b 11a 11b 12a 12b 13a 13b 14a 14b 15a 15b Figure 180, the ‘a’...
Page 746: Mvip, Byte Interleaving Two T1 Streams Onto A 4.096-Mbps Backplane
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor Figure 181. MVIP, Byte Interleaving Two T1 Streams onto a 4.096-Mbps Backplane 4.096 MHz clock Frame pulse x x x x x x x x x x x x...
Page 747 ® ® HSS Coprocessor—Intel IXP45X and Intel IXP46X Product Line of Network Processors Byte interleaving involves disregarding four in every 16 timeslots (as shown in Figure 182). The first four timeslots are unassigned except for the framing pulse. The following 4 bytes are byte 0 of each T1 frame. The next 4 bytes are byte 1 of each T1 frame.
Page 748: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—HSS Coprocessor ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Reference Number: 004US...
Page 749: Universal Asynchronous Receiver-Transmitter (Uart)
— and parallel-to-serial conversion — on data characters received from the Intel XScale processor. The Intel XScale processor, within the IXP45X/IXP46X network processors, can read the complete status of the UART at any time during functional operation. Available...
Page 750: Uart Timing Diagram
64-byte Receive FIFO, buffers data received from the serial link until the data is read by the Intel XScale processor. In Non-FIFO mode, data will be transmitted and received using two registers - the Transmit-Holding Register and the Receive-Buffer Register - along with the UART control, status and interrupt registers.
Page 751: Block Diagram
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors • Line break generation and detection • Internal diagnostic capabilities include: • Loopback controls for communications link fault isolation • Break, parity, overrun, and framing error simulation •...
Page 752 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Figure 184. UART Block Diagram ® Intel IXP46X Interrupt Network Processor Transmit Shift Reg Interrupt Control and Controller Status Registers Transmit Hold Register Transmit FIFO...
Page 753: Setting The Baud Rate
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 14.4.1 Setting the Baud Rate Each UART contains a programmable baud-rate generator that is capable of taking the 14.7456 MHz, input clock (clk_uart) and dividing it by any divisor ranging from 1 to 1).
Page 754 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) parity bit, and one or two stop bits (logic 1). The Line Control Register also contains a bit used for accessing the Divisor Latch Registers and causing a UART break condition.
Page 755: Uart Transmit Parity Operation
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 245 shows the serial output data configurations for transmission of the parity bit. Table 245. UART Transmit Parity Operation Data to be Transmitted Value of Parity Bit to be...
Page 756: Using The Modem Control Signals
The ability to loop back the transmit data path to the receive path allows the Intel XScale processor to verify the transmit data path and receive data path of the UART. The transmit interrupts, receive interrupts, and modem-control interrupts are operational, when placed in the loop-back diagnostic mode.
Page 757: Uart Interrupts
• CTS = logic 1 = CTS_N pin is 0 Modem Status Register Bit 0 is the Delta Clear-to-Send (DCTS). The Delta Clear-to- Send bit will inform the IXP45X/IXP46X network processors that nothing has happened to the Clear-to-Send Status since the last time that the Modem-Status Register was read.
Page 758 Receive FIFO or setting the RESETRF bit to logic 1, in the FIFO Control Register. If a Receive Character Time-Out Interrupt is active, the interrupt-time-out counter will be reset only after the IXP45X/IXP46X network processors read a character from the Receive FIFO. If a Receive Character Time-Out Interrupt is non-active, the interrupt...
Page 759 Receive FIFO. When the character at the bottom of the FIFO has errors, the Line Status error bits are set and are not cleared until the Intel XScale processor reads the Line Status Register. Even if the character in the FIFO is read —...
Page 760: Transmitting And Receiving Uart Data
IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Bits 7 and 5 are not implemented by the IXP45X/IXP46X network processors. The use of bit 7 through bit 4, of the Interrupt Enable Register, is defined differently from the register definition of standard 16550 UART.
Page 761: Uart Fifo Trigger Level
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 248. UART FIFO Trigger Level Interrupt Trigger Level [7:6] Description 1 byte or more in the FIFO causes an interrupt 8 bytes or more in the FIFO causes an interrupt...
Page 762: Interrupt Enable Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Table 249. Register Legend Attribute Legend Attribute Legend Read/Set Write Only Read/Write Not Accessible Normal Read Normal Read RW1C RW1S Write ‘1’ to clear Write ‘1’ to set The following sample register-summary table indicates, in parentheses, which paragraph tags are cross-referenced in the individual register tables.
Page 763: Transmit Holding Register
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register Bits Name Description 31:8 (Reserved) In non-FIFO mode, this register holds the character received by the UART’s Receive Shift Register. If fewer than 8 bits are received, the bits are right- justified and the leading bits are zeroed.
Page 764: Divisor Latch High Register
The DLAB bit in the Line Control Register must be set to logic 1 to access this register. 14.5.5 Interrupt Enable Register The DLAB bit in the Line-Control Register must be set to logic 0 to access this register. DMA is not supported on the IXP45X/IXP46X network processors. Register Name: 0xC800 X004 0x00000000 Hex Offset Address:...
Page 765: Interrupt Identification Register
DMA Requests Enable: 0 = DMA requests are disabled DMAE 1 = DMA requests are enabled Not used on IXP45X/IXP46X network processors UART Unit Enable: 0 = the unit is disabled 1 = the unit is enabled NRZ coding Enable:...
Page 766 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Priority Level Interrupt origin Receiver Time out occurred: It happens in FIFO mode only, when there is data in the receive FIFO but no activity for a time period.
Page 767: Uart Idd Bit Mapping
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 251. UART IDD Bit Mapping Interrupt ID Bits Interrupt SET/RESET Function Priority Type Source RESET Control None No Interrupt is pending Overrun Error, Parity Error,...
Page 768: Line Control Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Register Bits Name Description 31:8 (Reserved) Interrupt Trigger Level: When the number of entries in the receive FIFO equals the interrupt trigger level programmed into this field and the Received Data Available Interrupt is enabled (via IER), an interrupt is generated and appropriate bits are set in the IIR.
Page 769 ® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register Bits Name Description 31:8 (Reserved) Divisor Latch Access Bit: This bit must be set to logic 1 to access the Divisor Latches of the Baud Rate Generator during a READ or WRITE operation. It must...
Page 770: Modem Control Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) 14.5.9 Modem Control Register Register Name: 0xC800 X010 0x00000000 Hex Offset Address: Reset Hex Value: Register Modem Control Register Description: Access: Read/Write. (Reserved) Register (Sheet 1 of 2)
Page 771: Line Status Register
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register (Sheet 2 of 2) Bits Name Description Test bit: This bit is used only in loop-back test mode. OUT1 See LOOP row, above. Request to Send: This bit controls the Request to Send (RTS_N) output pin.
Page 772: Modem Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous Receiver-Transmitter (UART) Register (Sheet 2 of 2) Bits Name Description Break Interrupt: BI is set to a logic 1 when the received data input is held in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of Start bit + data bits + parity bit + stop bits).
Page 773: Scratch-Pad Register
® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register Name: 0xC800 X018 0x00000000 Hex Offset Address: Reset Hex Value: Register Modem Status Register Description: Access: Read Only. (Reserved) Register Bits Name Description 31:8...
Page 774: Infrared Selection Register
Infrared Data Association Serial Infrared Specification. In the IXP45X/IXP46X network processors, infrared mode is not supported. The reason for including this register in the address map and register description section is so software can ensure that this mode is never enabled.
Page 775 ® ® Universal Asynchronous Receiver-Transmitter (UART)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register (Sheet 2 of 2) Bits Name Description Transmit Pulse Width Select: When XMODE is set to 0, clocking of the IRDA transmit and receive logic is done by the UART clock, which must be operating in the 16X mode.
Page 776: Gpio Controller
IXP46X Product Line of Network Processors. The IXP45X/IXP46X network processors provide 16 general-purpose input/output pins for use in generating and capturing application specific input and output signals. Each pin can be programmed as either an input or output, and when GPIO0 through GPIO12 are programmed as an input, they can be used as an interrupt source.
Page 777: Theory Of Operation
Each register can be read through the APB interface and all registers except GPINR can be written through the APB interface. The GPIO on the IXP45X/IXP46X network processors can be configured to be used as general-purpose inputs or general-purpose outputs. Three 16-bit registers are used in order to configure, initialize, and use the general-purpose I/O.
Page 778: Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller the same bit in the General-Purpose Data Output Register — and the corresponding bit in the General-Purpose Enable Register is still set to a logic 0 — logic 0 will be replicated to the corresponding GPIO.
Page 779: Register Summary
® ® GPIO Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors The clock generation logic is reset using an early reset, early_reset_n – this reset is de- asserted prior to system reset being de-asserted. This ensures that GPIO15 provides a clock out while system reset is still asserted.
Page 780: Gpio Output Enable Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller GPOUTR Register Name: 0xC8004000 0x00000000 Physical Address: Reset Hex Value: I/O Output register. Controls output value of GPIO pins, depending on tri-state Register Description: control from GPOER.
Page 781: Gpio Input Register
® ® GPIO Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register GPOER Bits Name Description Reset Value Access 31: 16 (Reserved) Reads back 0 1 = Output pin is tri-stated or input (as clock is driven OE15...
Page 782: Gpio Interrupt Type Register 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller GPISR Register Name: 0xC800400C 0x00000000 Physical Address: Reset Hex Value: This register is used to store status of interrupts received on GP input pins Register Description: Access: Read/Write...
Page 783: Gpio Interrupt Type Register 2
® ® GPIO Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register GPIT1R (Sheet 2 of 2) Reset Bits Name Description Access Value gpio_npe_3 as per gpio_npe_7 gpio_npe_2 as per gpio_npe_7 gpio_npe_1 as per gpio_npe_7 gpio_npe_0 as per gpio_npe_7 000 –...
Page 784: Gpio Clock Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller Register GPIT2R Reset Bits Name Description Access Value 31:2 (Reserved) Not used. Ignored on writes and driven logic ‘0’ on reads. 23:2 GPIO15 Not used 20:1 GPIO14...
Page 785 ® ® GPIO Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register GPCLKR Reset Bits Name Description Access Value 31:2 (Reserved) Not used. Ignored on writes and driven logic ‘0’ on reads. 0 – Control from GPOUTR Register MUX15 1 –...
Page 786: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Reference Number: 306262-004US...
Page 787: Overview
Unit (PMU). These features aid in measuring and monitoring various system ® ® parameters that contribute to the overall performance of the Intel IXP45X and Intel IXP46X Product Line of Network Processors. Operation modes, setup mechanisms, registers, and interrupts are also described in this chapter.
Page 788: Occurrence Events
An occurrence event causes the counter to increase by one each time the event occurs. Table 254 presents the various occurrence events that are monitored on the IXP45X/ IXP46X network processors. Note that the PMU monitors two AHB buses, the north and south.
Page 789: Duration Events
® ® Performance Monitoring Unit (PMU)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 254. Occurrence Events Observe Monitored Event Description Interface Monitors the number of times a master is granted the bus. It increments the counter when the master is the bus initiator.
Page 790 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) • Split Transfer Latency — Represents the elapsed time between the Requester receiving a Split Response and the Split claimer transferring the first DWORD of Data Read.
Page 791: Performance Monitoring
Chapter 11.0, “Memory Controller” information on the semantics of these event signals. By setting up the IXP45X/IXP46X network processors system-level PMU registers, the following MCU performance parameters can be monitored: • Event type 0 : PMU registers ESR0, ESR1 programmed to 0x00000000 PCEC [0-7] contains the page miss counts for each of the 8 possible open pages of DDR SDRAM.
Page 792: Previous Master And Slave
Unit (PMU) • Event type 39: PMU registers ESR0, ESR1 programmed to 0x27272727 PCEC [0-7] contains the core memory bus read latency (from Intel XScale processor to DDR request to valid data back for each of the eight outstanding read requests possible from the Intel XScale processor to memory).
Page 793: Register Legend
Write ‘1’ to clear Write ‘1’ to set The performance monitoring facility on the IXP45X/IXP46X network processors consists of 13 memory-mapped registers for controlling operation and monitoring various events. Each register appears to be 32-bits wide to the APB bus. Each of these registers is accessed as a memory-mapped 32-bit register with a unique memory address.
Page 794: Event Select Registers
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) 16.6.1 Event Select Registers ESR0 and ESR1 The ESR controls the specific item being monitored. Each PECx field is programmed according to Table 260, “Event Mux Programming” on page 799.
Page 795: Pmu Status Register
® ® Performance Monitoring Unit (PMU)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register ESR (Sheet 2 of 2) Reset Bits Name Description Access Value 23:1 PEC6 ctrl Selects Enable conditions for counter PEC6. 0xFF 15:8 PEC5 ctrl Selects Enable conditions for counter PEC5.
Page 796: Programmable Event Counters
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) Register Name: 0xC800 2014 0x00000000 Physical Address: Reset Hex Value: Counter Enable Mode Register Register Description: Access: Read, Clear on write (Reserved) Register Reset Bits...
Page 797: Previous Master/Slave Register
® ® Performance Monitoring Unit (PMU)—Intel IXP45X and Intel IXP46X Product Line of Network Processors PECx Register Name: 0xC800 2020 0xC800 2024 0xC800 2028 0xC800 202C 0x00000000 Physical Address: Reset Hex Value: 0xC800 2030 0xC800 2034 0xC800 2038 0xC800 203C...
Page 798: Event Mapping
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) Register PMSR Reset Bits Name Description Access Value When set, the South AHB fields have captured an AHB error and these South fields are “stuck” at the first error condition. To clear the error, write a...
Page 799 ® ® Performance Monitoring Unit (PMU)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 259. AHB South PMU Mapping PMU Device # Name Master Slave Retry Split APB Bridge In the following table, note that there appear to be “too many” entries. For example, there is space allocated for 16 north AHB devices even though there may not be this many defined.
Page 800 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) Table 260. Event Mux Programming (Sheet 2 of 4) Even PEC0 PEC1 PEC2 PEC3 PEC4 PEC5 PEC6 PEC7 North North North North North North North...
Page 801 ® ® Performance Monitoring Unit (PMU)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 260. Event Mux Programming (Sheet 3 of 4) Even PEC0 PEC1 PEC2 PEC3 PEC4 PEC5 PEC6 PEC7 South South South South South South South...
Page 802 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Performance Monitoring Unit (PMU) Table 260. Event Mux Programming (Sheet 4 of 4) Even PEC0 PEC1 PEC2 PEC3 PEC4 PEC5 PEC6 PEC7 MPI[0] MPI[0] MPI[0] MPI[0] MPI[0] MPI[0] MPI[0]...
Page 803: Interrupt Controller
GPIO pins. The controller outputs both an IRQ and an FIQ interrupt to the Intel XScale processor. Any of the 64 input interrupts may be enabled to produce either the IRQ or FIQ output. The INTR_EN/INTR_EN2 Control Register(s) is used to enable an interrupt, and the INTR_SEL/INTR_SEL2 Control Register(s) can be programmed to present an interrupt as an IRQ or an FIQ.
Page 804: Intel Xscale Processor Interrupt Mapping
Int15 UART0 UART0 Interrupt Int16 Timer Time[3], Watchdog Timer Int17 APB PMU AHB Performance Monitoring Unit counter rollover ® Intel XScale Int18 Intel XScale processor PMU counter rollover Processor PMU Int19 GPIO GPIO[2] Int20 GPIO GPIO[3] Int21 GPIO GPIO[4] Int22...
Page 805 ® ® Interrupt Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® Table 261. Intel XScale Processor Interrupt Mapping (Sheet 2 of 2) Interrupt Default Source Description † Priority Int32 USB Host USB Host Interrupt Int33 I2C Interrupt...
Page 806: Interrupt Controller Block Diagram
The Interrupt Controller takes as inputs 63 individual interrupts (with interrupt 64 reserved). These 63 individual interrupts originate either from internal blocks on the IXP45X/IXP46X network processors or from dedicated GPIO pins. Interrupts are asserted if set (‘1’) and de-asserted if reset (‘0’).
Page 807: Interrupt Priority
The interrupts collected by the Interrupt Controller are combined and configured to be an FIQ interrupt or an IRQ. The FIQ signal going to the Intel XScale processor will be set when any of the interrupts assigned to be an FIQ become set. The IRQ signal going to the Intel XScale processor will be set when any of the interrupts assigned to be an IRQ are set.
Page 808: Assigning Fiq Or Irq Interrupts
The Interrupt Controller for the IXP45X/IXP46X network processors provides the capability to assign each interrupt as an FIQ or an IRQ interrupt. As discussed earlier, the Intel XScale processor only receives a single FIQ interrupt signal and a single IRQ interrupt signal.
Page 809: Enabling And Disabling Interrupts
For instance, interrupt number 0 is disabled and an interrupt occurs on interrupt number 0. The interrupt generated by interrupt number 0 will not be seen by the Intel XScale processor. The Interrupt-Enable Register is a pair of 32-bit registers that can individually enable or disable each of the 64 interrupts.
Page 810 Status Register and the result returned is a hexadecimal 0x00000001. The Interrupt Status Register is telling the Intel XScale processor that the interrupt number 0 (NPE A) has caused an interrupt and the interrupt is enabled as a FIQ interrupt.
Page 811: Interrupt Controller Memory Mapped Registers
® ® Interrupt Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors For example, interrupt number 1 (Ethernet NPE B) is the highest-priority IRQ interrupt, the value obtained when reading the IRQ Highest-Priority Interrupt Register would be hexadecimal 0x00000008. A value of 0 — returned when reading the IRQ Highest- Priority Register —...
Page 812: Interrupt Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Interrupt Controller Table 263. Interrupt Controller Memory Mapped Registers (Sheet 2 of 2) Address Access Name Description 0xC800300C INTR_IRQ_ST IRQ Status register 0xC8003010 INTR_FIQ_ST FIQ status Register 0xC8003014 INTR_PRTY...
Page 813: Interrupt Select Register
Physical Address: Reset Hex Value: ® This register decides if an interrupt is to be presented to the Intel XScale Processor as an Register FIQ or an IRQ. If a bit corresponding to an interrupt is set (to 1), that interrupt is presented Description: as a FIQ.
Page 814: Irq Status Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Interrupt Controller 17.6.4 IRQ Status Register INTR_ IRQ_ST Register Name: 0xC800 300C 0x00000000 Physical Address: Reset Hex Value: This register is an “AND” of the incoming status with the INTR_EN and the inverted version Register of the INTR_SEL.
Page 815: Interrupt Priority Register
® ® Interrupt Controller—Intel IXP45X and Intel IXP46X Product Line of Network Processors 17.6.6 Interrupt Priority Register INTR_PRTY Register Name: 0xC800 3014 0x00FAC688 Physical Address: Reset Hex Value: The highest eight priority interrupts can be programmed via this register, each of the 3-bit Register sets can be programmed to any priority from 0(000) through 7(111).
Page 816: Error High Priority Enable Register
Physical Address: Reset Hex Value: ® This register decides if an interrupt is to be presented to the Intel XScale Processor above all other Register priorities. This affects the priority only, not the number reported in the *_ENC_ST registers. Bit 0 of this Description: register corresponds to interrupt 32 and bit 31 corresponds to interrupt 63.
Page 817: Operating System Timer
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors 18.0 Operating System Timer 18.1 Overview The OST serves the function of a watchdog timer as well as a general-purpose timer and is capable of generating interrupts at predetermined intervals. The module contains several registers which are written and read via the APB interface.
Page 818: Operating System Timer Block Diagram
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Operating System Timer Figure 187. Operating System Timer Block Diagram pclk pclk Timestamp Timer sc_en Timestamp * Compare register prescale Ost Status Timestamp config * Register pclk General Purpose...
Page 819: Timestamp Timer Operation
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors to these registers has no effect unless ost_wdog_key = key_value. This is to prevent accidental writes to these registers. The typical operation would be for the software to...
Page 820: General-Purpose Timers Operation
• A 32-bit reload value register • A 16-bit prescale register • A 4-bit configuration register The purpose of the timers are to generate timed or periodic interrupts to the Intel XScale processor. Upon reset all the registers are initialized to zero.
Page 821: Register Summary
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors = 20ns * 26 * 24 = 12.48us If it is desirable to pause the timer, then use the tim0_pause_en to halt counting 4. ost_tim0_cfg <= 0x0F This will set tim0_pause_en To enable the counting such that the counter continues from its paused value 5.
Page 822: Register Summary
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Operating System Timer Table 265. Register Summary Counter Address Register Name Description Reset Value Attribute type “0xC8005024” “ost_ts_cmp” “Timestamp Compare Register” “0x00000000” “0xC8005028” “ost_ts_cfg” “Timestamp Configuration Register” “0x00000000” “0xC800502C”...
Page 823: General-Purpose Timer 0 Reload
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors 18.5.3 General-Purpose Timer 0 Reload ost_tim0_rl Register Name: 0xC8005008 0x00000000 Physical Address: Reset Hex Value: General-Purpose Timer 0 Reload Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 824: General-Purpose Timer 1 Reload
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Operating System Timer 18.5.5 General-Purpose Timer 1 Reload ost_tim1_rl Register Name: 0xC8005010 0x00000000 Physical Address: Reset Hex Value: General-Purpose Timer 1 Reload Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 825: Watchdog Enable Register
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors 18.5.7 Watchdog Enable Register ost_wdog_enab Register Name: 0xC8005018 0x00000000 Physical Address: Reset Hex Value: Watchdog Enable Register Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 826: Timestamp Compare Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Operating System Timer 18.5.9 Timer Status ost_status Register Name: 0xC8005020 0x00000000 Physical Address: Reset Hex Value: Timer Status Register Register Description: Access: Read/Write 1 to Clear 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 827: Timestamp Configuration Register
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors 18.5.11 Timestamp Configuration Register ost_ts_cfg Register Name: 0xC8005028 0x00000000 Physical Address: Reset Hex Value: Timestamp Configuration Register Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 828: General-Purpose Timer 0 Configuration Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Operating System Timer 18.5.13 General-Purpose Timer 0 Configuration Register ost_tim0_cfg Register Name: 0xC8005030 0x00000000 Physical Address: Reset Hex Value: General-Purpose Timer 0 Configuration Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 829: General-Purpose Timer 1 Configuration Register
® ® Operating System Timer—Intel IXP45X and Intel IXP46X Product Line of Network Processors 18.5.15 General-Purpose Timer 1 Configuration Register ost_tim1_cfg Register Name: 0xC8005038 0x00000000 Physical Address: Reset Hex Value: General-Purpose Timer 1Configuration Register Description: Access: Read/Write 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 830: Time Synchronization Hardware Assist (Tsync)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.0 Time Synchronization Hardware Assist (TSYNC) 19.1 Overview In a distributed control system containing multiple clocks, individual clocks tend to drift apart. Some kind of correction mechanism is necessary to synchronize the individual clocks to maintain global time, which is accurate to some requisite clock resolution.
Page 831: Block Diagram Of Tsync Circuit
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 188. Block Diagram of TSync Circuit Control/Status - 32 bit Event - 32 bit Carry Accumulator - 32 bit Addend - 32 bit...
Page 832: Time Stamp Reference Point
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) synchronization delays, the actual timestamp will be slightly later than the desired reference point. However, allowing for 1 pclk synchronization jitter, this is a fixed delay, easily nulled out in the software portion of the algorithm.
Page 833: Ipv6 Compatibility
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Delay_Req Message 19.3.4 Firmware in a time slave can transmit a Delay_Req message to the master for the purpose of determining propagation delays in the network. A Delay_Req message is defined as a value of 0x01 in byte 74 of the Ethernet frame after the start of frame delimiter.
Page 834: System Time Clock Rates
Event register. No interrupt ® is sent to the Intel XScale Processor upon timestamp capture/lock on the MII interface, this is due to being to early as the MII messages would not have propagated up the network protocol stack, thus the poling of the event register is necessary to determine if the timestamp is captured.
Page 835: Errors In Messages
TSync logic to be ignored. Note: On the IXP45X/IXP46X network processors, the TSync logic does not check if properly formatted messages have PHY errors. ®...
Page 836: Master Mode Programming Considerations
Write ‘1’ to clear Write ‘1’ to set 19.5.1 Register Map The registers of the TSync registers reside within the memory map of the IXP45X/ IXP46X network processors. Table 268 presents the address offset for the TSync registers, the names and mnemonics of the registers, and their access capability.
Page 837: Register Summary Table
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 268. Register Summary Table (Sheet 1 of 2) Address Offset Function Mnemonic Access paddr[11:0] Time Sync Control TS_Control Time Sync Event TS_Event Addend...
Page 838: Register Descriptions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) Table 268. Register Summary Table (Sheet 2 of 2) Address Offset Function Mnemonic Access paddr[11:0] SequenceID2/SourceUUID2_High TS_SrcUUID2Hi 0A0-0BF Reserved for Channel 3 0C0-0DF Reserved for Channel 4...
Page 839: Time Sync Control Register
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.1 Time Sync Control Register TS_Control Register Name: Block RegBlockAddress 0x000 x0000 Offset Address Reset Value Base Address: Time Sync Control Register Register Description: Access: (See below.)
Page 840: Time Sync Event Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.2 Time Sync Event Register TS_Event Register Name: Block RegBlockAddress 0x004 x0010 Offset Address Reset Value Base Address: Time Sync Event Register Register Description: Access: (See below.)
Page 841: Accumulator Register
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register TS_Addend Reset Bits Name Description Access Value The Addend register contains the frequency scaling value used by a firmware algorithm to achieve time synchronization in the module. The value in this register is added to the value in the Accumulator.
Page 842: Test Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.5 Test Register TS_Test Register Name: Block RegBlockAddress 0x010 x000 Offset Address Reset Value Base Address: Time Sync Test Register Register Description: Access: (See below.)
Page 843: Rawsystemtime_Low Register
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.6 RawSystemTime_Low Register TS_RSysTimeLo Register Name: Block RegBlockAddress 0x018 Offset Address Reset Value Base Address: RawSystemTime_Low Register Register Description: Access: (See below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 844: Systemtime_Low Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.8 SystemTime_Low Register TS_SysTimeLo Register Name: Block RegBlockAddress 0x020 Offset Address Reset Value Base Address: SystemTime_Low Register Register Description: Access: (See below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 845: Targettime_High Register
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.10 TargetTime_Low Register TS_TrgtLo Register Name: Block RegBlockAddress 0x028 Offset Address Reset Value Base Address: TargetTime_Low Register Register Description: Access: (See below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 846: Auxiliary Slave Mode Snapshot Low Register – Asms_Low
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.12 Auxiliary Slave Mode Snapshot Low Register – ASMS_Low TS_ASMSLo Register Name: Block RegBlockAddress 0x030 Offset Address Reset Value Base Address: Auxiliary Slave Mode Snapshot Low Register...
Page 847: Auxiliary Master Mode Snapshot Low Register – Amms_Low
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.14 Auxiliary Master Mode Snapshot Low Register – AMMS_Low TS_AMMSLo Register Name: Block RegBlockAddress 0x038 Offset Address Reset Value Base Address: Auxiliary Master Mode Snapshot Low Register...
Page 848: Ts_Channel_Control Register (Per Channel)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.16 TS_Channel_Control Register (Per Channel) TS_Ch_Control Register Name: Block RegBlockAddress 0x040* Offset Address Reset Value Base Address: Time Synchronization Channel Control Register Register Description: Access: (See below.)
Page 849: Ts_Channel_Event Register (Per Channel)
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.17 TS_Channel_Event Register (Per Channel) TS_Ch_Event Register Name: Block RegBlockAddress 0x044* Offset Address Reset Value Base Address: Time Synchronization Channel Event Register Register Description: Access: (See below.)
Page 850: Xmit_Snapshot_Low Register (Per Channel)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.18 XMIT_Snapshot_Low Register (Per Channel) TS_TxSnapLo Register Name: Block RegBlockAddress 0x048* Offset Address Reset Value Base Address: Transmit Snapshot Low Register Register Description: Access: (See below.)
Page 851: Xmit_Snapshot_High Register (Per Channel)
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.19 XMIT_Snapshot_High Register (Per Channel) TS_TxSnapHi Register Name: Block RegBlockAddress 0x04C* Offset Address Reset Value Base Address: Transmit Snapshot High Register Register Description: Access: (See below.)
Page 852: Recv_Snapshot Low Register (Per Channel)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.20 RECV_Snapshot Low Register (Per Channel) TS_RxSnapLo Register Name: Block RegBlockAddress 0x050* Offset Address Reset Value Base Address: Receive Snapshot Low Register Register Description: Access: (See below.)
Page 853: Recv_Snapshot High Register (Per Channel)
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.21 RECV_Snapshot High Register (Per Channel) TS_RxSnapHi Register Name: Block RegBlockAddress 0x054* Offset Address Reset Value Base Address: Receive Snapshot High Register Register Description: Access: (See below.)
Page 854: Sourceuuid0_Low Register (Per Channel)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) 19.5.2.22 SourceUUID0_Low Register (Per Channel) TS_SrcUUID0Lo Register Name: Block RegBlockAddress 0x058* Offset Address Reset Value Base Address: Source UUID0 Low Register Register Description: Access: (See below.)
Page 855: Sequenceid/Sourceuuid_High Register (Per Channel)
® ® Time Synchronization Hardware Assist (TSYNC)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 19.5.2.23 SequenceID/SourceUUID_High Register (Per Channel) When a Delay_Req message in Master mode, or a Sync message in Slave mode, is received, the source UUID and the sequence ID of the message are captured.
Page 856: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization Hardware Assist (TSYNC) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 857: Synchronous Serial Port
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors 20.0 Synchronous Serial Port The Synchronous Serial Port (SSP) is a full-duplex synchronous serial interface. It can connect to a variety of external analog-to-digital (A/D) converters, audio and telecom codecs, and many other devices that use serial protocols for transferring data.
Page 858: Data Formats
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port 20.2 Data Formats 20.2.1 Serial Data Formats for Transfer to/from Peripherals Four pins are used to transfer data between the CPU and external codecs or modems.
Page 859: Texas Instruments* Synchronous Serial Frame Format
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors 20.2.1.1 SSP Format — Detail When outgoing data in the SSP controller is ready to transmit, SSP_SFRM asserts for one clock period. On the following clock, data to be transmitted is driven on SSP_TXD one bit at a time, most significant bit first.
Page 860 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port For SPI format, SSP_SCLK and SSP_TXD are low, and SSP_SFRM is high, in idle mode or when the SSP is disabled. When transmit (outgoing) data is ready, SSP_SFRM goes low and stays low for the remainder of the frame.
Page 861: Motorola* Spi Frame Format
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 271. Motorola SPI Frame Format SSP_ SCLK SSP_S SSP_T Bit<N.. Bit<N> Bit<1> Bit<0> 1> SSP_R Bit<N.. Bit<N> Bit<1> Bit<0> 1> 4 to 16 Bits Single Transfer...
Page 862: Parallel Data Formats For Buffer Storage
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Table 272. National Microwire Frame Format Bit<7> Bit<0> 8-Bit Control 1 Clk Bit<N> Bit<0> 4 to 16 Bits Single Transfer Bit<0> Bit<7> Bit<0> 1 Clk 1 Clk Bit<N>...
Page 863: Ssp Serial Port Register Summary
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors Each buffer consists of a dual-port register file with control circuitry to make it work as a FIFO, with independent read and write ports. Buffer filling and emptying may be performed by the system processor in response to an interrupt from the FIFO logic.
Page 864: Ssp Control Register 0 (Sscr)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Table 274. Register Legend Attribute Legend Attribute Legend Reserved Read Clear Preserved Read Only Read/Set Write Only Read/Write Not Accessible Normal Read Normal Read RW1C RW1S Write ‘1’...
Page 865: Serial Clock Rate (Scr)
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors When the SSE bit is cleared during active operation, the SSP is disabled immediately, causing the current frame being transmitted to be terminated. Clearing SSE resets the SSP’s FIFOs.
Page 866: Ssp Control Register 1 (Sscr)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Register SSCR0 (Sheet 2 of 2) Reset Name Description Access Value This field specifies the Data Size Selection. 0000 - Reserved, undefined operation 0001 - Reserved, undefined operation...
Page 867: Motorola* Spi Frame Formats For Spo And Sph Programming
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors 20.5.2.4 Serial Clock Polarity (SPO) The serial clock (SSP_SCLK) polarity bit (SPO) selects the polarity of the inactive state of the SSP_SCLK pin when Motorola SPI format is selected (FRF=00). For SPO=0, the SSP_SCLK is held low in the inactive or idle state when the SSP is not transmitting/ receiving data.
Page 868: National Microwire* Data Size (Mwds)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Table 275. Motorola SPI Frame Formats for SPO and SPH Programming (Sheet 2 of 2) SSP_S SPO=1 SSP_S SSP_T Bit<N> Bit<N..> Bit<1> Bit<0> SSP_R Bit<N> Bit<N..>...
Page 869: Ssp Status Register
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors SSCR1 Register Name: Block 0xC801_20 0x04 0x0000_0000 Offset Address Reset Value Base Address: SSC Control Register 1 Register Description: Access: (See below.) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9...
Page 870: Transmit Fifo Service Request Flag (Tfs) (Read-Only, Maskable Interrupt)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Bits that cause an interrupt will signal the request as long as the bit is set. Once the bit is cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags.
Page 871: Transmit Fifo Level (Tfl)
® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors the ROR bit is asserted, and the newly received data is discarded. This process is repeated for each new piece of data received until at least one empty FIFO entry exists.
Page 872: Ssp Interrupt Test Register (Ssitr)
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port Register SSSR (Sheet 2 of 2) Bits Name Description Reset Value Access SSP is busy 0 = SSP is idle or disabled 1 = SSP currently transmitting or receiving a frame Receive FIFO not empty.
Page 873 ® ® Synchronous Serial Port—Intel IXP45X and Intel IXP46X Product Line of Network Processors For outbound data transfers (WRITE from system to SSP peripheral), the register may be loaded (written) by the system processor anytime it is empty. When a data size of less than 16-bits is selected, the user should not left-justify data written to the transmit FIFO.
Page 874: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Synchronous Serial Port ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 875: I2C Bus Interface Unit
C unit. 21.1 Overview The I C Bus Interface Unit allows the IXP45X/IXP46X network processors to serve as a master and slave device residing on the I C bus. The I C bus is a serial bus developed by Phillips Corporation* consisting of a 2-pin interface. SDA (Serial Data/Address) is...
Page 876: C Bus Interface Unit Block Diagram
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit The I C unit’s state machines and functionality are partially controlled by using local memory mapped registers (MMRs) that store configuration and operation information. The registers are controlled from the APB bus and reside in the i2c_registers block.
Page 877: C Bus Configuration Example
C transactions are either initiated by the IXP45X/IXP46X network processors as a master or are received by the IXP45X/IXP46X network processors as a slave. Both conditions may result in the processor doing reads, writes, or both to the I C bus.
Page 878: Modes Of Operation
C Bus Interface Unit is in idle mode (neither receiving or transmitting serial data), the unit defaults to Slave-Receive mode. This allows the interface to monitor the bus and receive any slave addresses that might be intended for the IXP45X/IXP46X network processors.
Page 879: Start And Stop Bus States
“Slave Operations” on page 889. When the IXP45X/IXP46X network processors want to initiate a read or write on the I bus, the I C Bus Interface Unit will transition from the default Slave-Receive mode to Master-Transmit mode.
Page 880: Start And Stop Conditions
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit Figure 192. START and STOP Conditions Stop Condition Start Condition B4257-01 21.4.3.1 START Condition The START condition (bits 1:0 of the ICR set to 2’b01) initiates a master transaction or repeated START.
Page 881: Stop Condition
Serial Clock Line (SCL) Generation The I C unit of the IXP45X/IXP46X network processors is required to generate the I clock output when in master mode (either receive or transmit). SCL clock generation is accomplished through the use of the ICCR value, which is programmed at initialization.
Page 882: Data And Addressing Management
I C unit performs the necessary clock synchronization. Note: The ICCR register is reserved on the IXP45X/IXP46X network processors. The I C unit’s master driver clock, SCL, has the option of running at 100-Kbps or 400-Kbps. This is...
Page 883: Data Format Of First Byte In Master Transaction
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 194. Data Format of First Byte in Master Transaction Read/Write Transaction (0) Write (1) Read Slave 7-Bit Address B4259-01 The first byte transmission must be followed by an Ack pulse from the addressed slave.
Page 884: Acknowledge On The I
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit receiving each byte from the serial bus. Before receiving the last byte, software must set the Ack/Nack Control bit to Nack. Nack is then sent after the next byte is received to indicate the last byte.
Page 885: Clock Synchronization During The Arbitration Procedure
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors SCL line. Masters with shorter periods are held in a high wait-state during this time. Once the master with the longest period completes, the SCL line transitions to the high state, masters with the shorter periods can continue the data cycle.
Page 886: Master Operations
I C unit has the option of two master modes: • Master-Transmit — The IXP45X/IXP46X network processors write data • Master-Receive — The IXP45X/IXP46X network processors read data The CPU initiates a master transaction by writing to the ICR register. Data is read and written from the I C unit through the memory-mapped registers.
Page 887: Master Transactions
• Occurs when the IDBR Transmit Empty ISR bit is set and the Transfer Byte bit is clear. If enabled, the IDBR Transmit Empty Write one data Master-transmit Interrupt is signalled to the IXP45X/IXP46X network processors. byte to the only •...
Page 888: Master-Receiver Read From Slave-Transmitter
Interrupt is signalled to the CPU. • When the IDBR is read, if the Ack/Nack Status is clear (indicating Ack), the IXP45X/IXP46X network processors will write the Ack/ Nack Control bit and set the Transfer Byte bit to initiate the next...
Page 889: Master-Receiver Read From Slave-Transmitter / Repeated Start
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 199. Master-Receiver Read from Slave-Transmitter / Repeated Start / Master-Transmitter Write to Slave-Receiver Slave R/W# Data Data Slave R/W# Data Data START STOP Address...
Page 890 IXP45X/IXP46X network processors. IDBR • The IXP45X/IXP46X network processors will write a data byte to the IDBR and set the Transfer Byte bit to initiate the transfer. • As a slave-transmitter, the I C Bus Interface Unit is responsible for...
Page 891: Master-Transmitter Write To Slave-Receiver
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 201. Master-Transmitter Write to Slave-Receiver R /W # D ata D ata S TAR T Slave Ad dress A CK A CK A CK...
Page 892: Write N Bytes As A Slave
• Sets the ISR general call address detected bit • Sets the ISR slave address detected bit • Interrupts (when enabled) the IXP45X/IXP46X network processors If the I C unit receives a general call address and the ICR General Call Disable bit is set, the I C unit ignores the general call address.
Page 893: Read N Bytes As A Slave
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors Read ISR: Slave Address Detected (1), Unit Busy (1), R/nW# bit (1), Ack/Nack (0) 2. Write a 1 to the ISR[Slave Address Detected] bit to clear the interrupt.
Page 894: Write 1 Byte As A Master
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit 21.7 Master Programming Examples 21.7.1 Initialize Unit 1. Write ISAR: Set slave address. 2. Write ICR: Enable all interrupts (except Arb Loss), set SCL Enable, set Unit Enable and enable the I 21.7.2...
Page 895: Write 2 Bytes And Repeated Start Read 1 Byte As A Master
® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors 21.7.4 Write 2 Bytes and Repeated Start Read 1 Byte as a Master 1. Write IDBR: Target slave address and R/W# bit (0 for write).
Page 896: Glitch Suppression Logic
3. Clear reset in the ICR. 21.10 Register Definitions The following registers are associated with the I C Bus Interface Unit. They are all located within the peripheral memory-mapped address space of the IXP45X/IXP46X network processors. ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual...
Page 897: C Register Addresses
0xC801_1014 IBMR “I2C Bus Monitor Register - IBMR” on page 902 21.10.1 C Control Register - ICR The IXP45X/IXP46X network processors use the bits in the I C Control Register (ICR) to control the I C unit. C Control Register...
Page 898 STOP. The Transfer Byte bit (03) must remain clear. In master-receive mode, when a Nack is sent without a STOP (STOP ICR bit was not set) and the IXP45X/IXP46X network processors do not send a repeated START, setting this bit sends the STOP. Once again, the Transfer Byte bit (03) must remain clear.
Page 899 1 = Send a START. 21.10.2 C Status Register - ISR C interrupts are signalled to the interrupt controller of the IXP45X/IXP46X network processors by the I C Interrupt Status Register (ISR). Software uses the ISR bits to check the status of the I C unit and bus.
Page 900 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit Register Bits Name Description Reset Value Access 31:1 — (Reserved) 000000H — Bus Error Detected: 0 = No error detected. 1 = The I C unit sets this bit when it detects one of the following error conditions: •...
Page 901 The I C Slave Address Register defines the I C unit’s 7-bit slave address to which the IXP45X/IXP46X network processors respond when in slave-receive mode. This register is written by the processor before enabling I C operations. The register is fully...
Page 902 IDBR and sets the Transfer Byte bit. When the I C Bus Interface Unit is in receive mode (master or slave), the IXP45X/ IXP46X network processors will read IDBR data over the internal bus. This occurs when the IDBR Receive Full Interrupt is signalled.
Page 903 ® ® I2C Bus Interface Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors C Bus Monitor Register - IBMR Register Name: Block 0xC801_1014 0x0000_0000 Offset Address Reset Value Base Address: OffsetAddress C Bus Monitor Register - IBMR Register Description: Access: (See below.)
Page 904 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 905: Public Key Exchange Crypto Engine
® ® Public Key Exchange Crypto Engine—Intel IXP45X and Intel IXP46X Product Line of Network Processors 22.0 Public Key Exchange Crypto Engine The Public Key Exchange (PKE) Crypto Engine is used to accelerate the establishment of secure connections by accelerating the key exchange process. This particular implementation consists of four main components: •...
Page 906 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Public Key Exchange Crypto Engine ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 907: Ahb-Pke Bridge
• Decode of address bits 16:8 to select a peripheral on the PKE bus • Support up to a 4KB EAU ram space • Additionally the EAU and SHA blocks will generate interrupts to the Intel XScale processor. (eau_int, sha_int) ®...
Page 908: Ahb-Pke Bridge Block Diagram
RSA Bus B4317-01 23.4 Theory of Operation The function of the AHB-PKE Bridge is to pass data between the Intel XScale processor AHB master and PKE Bus slaves. 23.4.1 Peripheral Information Each PKE peripheral is selected by a PKE_sel_xxx signal that is active whenever an address is within the peripheral’s address space.
Page 909 ® ® AHB-PKE Bridge—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 284. PKE Peripheral Memory Map and Access Information Address Range Peripheral PSEL name PRDATA signal name 7000_2101 – (Reserved) 7000_01FF 7000_2200 – SHA MMR PKE_sel_sha sha_rdata 7000_22FF 7000_2300 –...
Page 910 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB-PKE Bridge ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 911: Random Number Generator
® ® Random Number Generator—Intel IXP45X and Intel IXP46X Product Line of Network Processors 24.0 Random Number Generator 24.1 Theory of Operation The Random Number Generator (RNG) unit provides a digital, random-number- generation capability. The Random Number Generator (RNG) produces a series of random numbers for use in, among other things, key generation.
Page 912: Random Number Fifo
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Random Number Generator 24.2.1 Registers 24.2.1.1 Random Number FIFO RNG_FIFO Register Name: Block 0x7000 _2100 Unknown Offset Address Reset Value Base Address: FIFO containing random numbers generated by the RNG. After a...
Page 913: Exponentiation Acceleration Unit
Intel XScale processor must serialize the required operations to the EAU. The EAU begins operating after the Intel XScale processor has moved data into the EAU RAM and loads the EAU’s command register with an appropriate command. After executing the command, the EAU appropriately sets its status bits and waits idle until it receives another command from the Intel XScale processor.
Page 914: Exponentiation Acceleration Unit: Block Diagram
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Exponentiation Acceleration Unit 25.3 Block Diagram Figure 206. Exponentiation Acceleration Unit: Block Diagram Control Lines Address 2KB 3-ported RAM Decode Address Range Selects Data Control & Calc Status EAU I/F...
Page 915: Eau Command Register
® ® Exponentiation Acceleration Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors 25.3.2 EAU RAM Writes Writes to the EAU RAM are buffered. The buffering occurs on a word (32-bit) basis. EAU RAM writes signal completion of a write using the same signaling protocol described for EAU RAM Reads.
Page 916 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Exponentiation Acceleration Unit Register EAU Command Register Reset Bits Name Description Access Value 31:3 (Reserved) 0x00 EAU Short Exponent Enabled • 0: do NOT skip leading zeros in modular exponentiation operation •...
Page 917: Eau Status Register
® ® Exponentiation Acceleration Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors 25.4.2 EAU Status Register EAUSTAT Register Name: Block 0x7000 _2004 0x0000_0000 Offset Address Reset Value Base Address: The EAU Status Register is a single byte used to read the status of...
Page 918: Eau Interrupt Register
Reads to the RAM are also buffered and accessed with different timing than reads to registers. Reading values from the EAU takes several cycles, and during this time the Intel XScale processor is held off. using EAU_DONE. The EAU RAM resides at memory locations as shown in Table 290, “EAU RAM Memory Locations”...
Page 919: Performance Requirements
® ® Exponentiation Acceleration Unit—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 290. EAU RAM Memory Locations Address Offset MonPro Modular Modular Big number Big Number Copy, from EAU RAM (R= a_bar * Exponentiation Reduction Multiplication Add, Sub...
Page 920 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Exponentiation Acceleration Unit ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...
Page 921: Block Diagram
The hashing unit (SHA) is used to accelerate digital signature computations and to ® whiten the RNG output. It is the responsibility of the Intel XScale Processor to get the data from the RNG, provide it to the SHA unit, and retrieve the data after it is complete.
Page 922: Hash Configuration Register
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Hashing Unit (SHA) Table 292. Hashing Coprocessor: Register Summary (Sheet 2 of 2) Block Offset Page Register Name Description Reset Value Access Address Address Number 0x7000_ 2208 Hash_Int Hash Interrupt Register...
Page 923: Hash Interrupt Register
® ® Hashing Unit (SHA)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register Hash_Do Reset Bits Name Description Access Value 31:1 (Reserved) These bits are always 0. Hash Do 1: Begin Hash Computation 26.4.3 Hash Interrupt Register Hash_Int...
Page 924: Hash Data Fifo
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Hashing Unit (SHA) 26.4.5 Hash Data FIFO Hash_Data Register Name: Block 0x7000_ 2210 0x00000000 Offset Address Reset Value Base Address: Hashing Coprocessor Data Register Register Description: Access: (See below.)
Page 925 ® ® Hashing Unit (SHA)—Intel IXP45X and Intel IXP46X Product Line of Network Processors ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors August 2006 Developer’s Manual Reference Number: 306262-0014US...
Page 926: Overview
NPEs and Intel XScale processor (or any other AHB bus master), a Flag Bus interface, an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale processor. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM.
Page 927: Ahb Queue Manager
• Provides Underflow and Overflow Status Flags for each of the queues 0-31 • Programmable event status enable for queues 32-63 • Two Intel XScale processor interrupts, one for queues 0-31 and one for queues 32- • Individual interrupt enables for each queue •...
Page 928: Ahb Queue Manager Memory Map
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) are necessarily constrained to occur in the order they occur on the AHB. The timing between an AHB operation and a flag bus update is fixed. Not all NPEs are required to be connected to the flag bus via their CCP, so this connection scheme is very flexible.
Page 929: Queue Control
® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Table 293. AHB Queue Manager Memory Map (Sheet 2 of 2) 0x0043C Queue 0 to 63 Interrupt Register 2 x 4 Bytes 0x00438 0x00434 Queue 0 to 63 Interrupt Enable Register...
Page 930 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) • Queue Size(128 words)/Queue Entry Size(4 words) = 32 entries of 4 words each • Queue Size(128 words)/Queue Entry Size(2 words) = 64 entries of 2 words each •...
Page 931: Representative Logical Diagram Of A Queue
® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Figure 208. Representative Logical Diagram of a Queue Queue Size Queue SRAM DOUT Flag Remap (lower queues) Queue Mapping Flag Strb Queue # Flag Queue Id...
Page 932 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) To access any given queue, after the selected queue configuration is read from SRAM, the queue base address is summed with the read or write pointer to form the queue address.
Page 933: Queue Status
32-63. The Flag Bus will communicate status for queues 0-31 to the NPEs, the status funnel will communicate status for queues 32-63 to the event inputs to the NPEs, and two interrupts will provide status interrupting capability for the Intel XScale processor. The following sections outline the queue status requirements. 27.4.2.1...
Page 934: Queue Status Flags
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) Table 294. Queue Status Flags Nearly Empty Nearly Full # Entries in the Watermark Watermark Queue 0 (000) 0 (000) 1 – 63 1 (001) 1 (001) 2 –...
Page 935: Aqm Sram
A parity error may be signaled via an interrupt to the Intel XScale processor or some other mechanism. When the Error bit in the QUEADDERR register is true the aqm_parity_error port is true, and remains true until the Error bit is cleared.
Page 936: Data Validity Cases And Their Handling
(if anything) can be done. Table 295. Data Validity Cases and Their Handling Hardware Case Software Signal Recovery Signal ® Data Abort fault to Intel XScale Processor Error to AHB COP Unsupported bus AHB Error Target Abort to PCI None operation response...
Page 937: Burst Operations To Queues
® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors On the overflow condition, the written data is permanently lost. On the underflow condition, the data returned is zero. If there are parity errors where the parity notification is not enabled, the data returned represents the data containing the parity error.
Page 938 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) Table 297. Register Summary (Sheet 2 of 2) Address Register Name Description Reset Value Access 0x600003F0 QUEACC63_0 Queue 63word 0 data register Queue 63 word 1 data register (used only when Queue 63...
Page 939: Queue Access Word Registers 0 - 63
® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 27.6 Register Descriptions 27.6.1 Queue Access Word Registers 0 - 63 External agents wanting to access a queue, will perform an AHB read or write to the Queue Access Register locations.
Page 940: Underflow/Overflow Status Register 0 - 1
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) Register QUELOWSTAT (0 <= n <=3) Reset Bits Name Description Access Value (0 <= k <= 7) Queue (8n+k) complete status flags of: Queue(8n+k 4k+3...
Page 941 ® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors Register QUEUPPSTATE Reset Bits Name Description Access Value Empty (0 <= k <= 31) Queue (k) Empty Status Flag. 27.6.5 Queues 32-63 Nearly Empty Status Register The access to these status registers is read/write, however except for diagnostic and test purposes, normal operation to these registers should be read only.
Page 942 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) 27.6.6 Queues 32-63 Nearly Full Status Register The access to these status registers is read/write, however except for diagnostic and test purposes, normal operation to these registers should be read only. Writing status does not actually change the status, it only writes the shadow register which contains the status.
Page 943 ® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors INT0SRCSELREG (0 <= n <=3) Register Name: Block Reg #n 0x0420 + 4n 0x00000000 Offset Address Reset Value Base Address: Status Flag selection for interrupt 0 source on queues 0-31.
Page 944 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) 27.6.9 Queue Interrupt Enable Register 0 – 1 QUEIEREG(0 <= n <=1) Register Name: Block 0x0430 + 4n 0x00000000 Offset Address Reset Value Base Address: Interrupt enables for the queues 0-63.
Page 945 ® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 27.6.11 Queue Configuration Words 0 - 63 The 64 queue configuration words are located in internal SRAM and require initialization before AQM usage. The read and write pointers need to be cleared on initialization, because this reflects an empty queue.
Page 946 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) 27.6.12 Queue 32 to 63 Event ‘A’ Enable Register This register contains a bit map which enables the chosen class of events (via the Event Source Select Register) through the Event ‘A’...
Page 947 ® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors QUEUPPEVC Register Name: Block 0x0450 + 4n 0x00000000 Offset Address Reset Value Base Address: Queue Event output ‘C’ enable register. Register Description: Access: (See below.)
Page 948 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) 27.6.16 Queue 0 to 31 Status Selection Map Register QUELOSTATMAP Register Name: Depends on Block 0x045C + 4n AQM instanti- Offset Address Reset Value Base Address: ation Queue Status Selection register.
Page 949 ® ® AHB Queue Manager (AQM)—Intel IXP45X and Intel IXP46X Product Line of Network Processors 27.6.17 Queue SRAM Error Data Register QUEDATAERR Register Name: Block 0x0464 + 4n Not Applicable Offset Address Reset Value Base Address: Queue SRAM Parity Error Data Register.
Page 950 ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—AHB Queue Manager (AQM) ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Reference Number: 306262-004US...
Page 951: Memory Controller Unit (Mcu), Multiple-Bit, Ecc Error
• Attempts to access units with types of accesses the units are not designed to accept (such as INCR 16 for many IXP45X/IXP46X network processors), or • Data Corruption in the target, indicated by either parity errors or uncorrectable ECC errors in memory.
Page 952 AHB error will be sending an interrupt to the Interrupt Controller. This allows the Intel XScale processor to know that an error condition exists, and attempt to solve in whatever manner determined appropriate for the given system.
Page 953: Npe Error Handling Illustration
IXP45X and Intel IXP46X Product Line of Network Processors Table 298 on page 953 displays the types of coprocessor errors that can be generated to each NPE contained within the IXP45X/IXP46X network processors. Table 298. NPE Coprocessor Error Defined Coprocessor Errors...
Page 954 NPE core stops execution. The NPE also asserts an interrupt to the Intel XScale processor. In addition, the NPE core will indicate to the Coprocessors that an error happened (NPE error). The error indication to the coprocessors is sticky and will be deasserted only on resetting the NPE core.
Page 955 CAM, the SWCP will indicate unsuccessful completion of operation and will not lock-up. ® But the SWCP will assert an interrupt to the Intel XScale Processor indicating the parity error. Other Coprocessors In case of a parity error, continue operation without locking up.
Page 956 Reset state The HSS Coprocessor will be in reset state. The HSS pins will be tri- stated. So the framer can potentially lose sync with the IXP45X/IXP46X network processors. The recommendation is that the HSS framer is also reset at the same time the NPE is soft reset. This could be accomplished by utilizing the GPIO pins on the IXP45X/IXP46X network processors or through other system mechanisms.
Page 957: Expansion Bus Controller Response To Errors
MCU interface, it transition to its fault handler. A second such error can irretrievably lose the program counter, causing unpredictable system results. This is the inherent nature of the ARM* architecture which is not altered by the IXP45X/IXP46X network processors.
Page 958: Developer's Manual August
® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors—Error Handling ® ® Intel IXP45X and Intel IXP46X Product Line of Network Processors Developer’s Manual August 2006 Order Number: 306262-004US...

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