Intel IXP45X Developer's Manual page 417

USB 2.0 Host Controller—Intel
several micro-frames of activity on the port until the host controller evaluates the
Suspend bit. The host controller must evaluate the Suspend bit at least every frame
boundary.
System software can initiate a resume on a selectively suspended port by writing a one
to the Force Port Resume bit. Software should not attempt to resume a port unless the
port reports that it is in the suspended state (see
page 382). If system software sets Force Port Resume bit to a one when the port is not
in the suspended state, the resulting behavior is undefined. In order to assure proper
USB device operation, software must wait for at least 10 milliseconds after a port
indicates that it is suspended (Suspend bit is a one) before initiating a port resume via
the Force Port Resume bit. When Force Port Resume bit is a one, the host controller
sends resume signaling down the port. System software times the duration of the
resume (nominally 20 milliseconds) then sets the Force Port Resume bit to a zero.
When the host controller receives the write to transition Force Port Resume to zero, it
completes the resume sequence as defined in the USB specification, and sets both the
Force Port Resume and Suspend bits to zero. Software-initiated port resumes do not
affect the Port Change Detect bit in the USBSTS register nor do they cause an interrupt
if the Port Change Interrupt Enable bit in the USBINTR register is a one. An external
USB event may also initiate a resume. The wake events are defined above. When a
wake event occurs on a suspended port, the resume signaling is detected by the port
and the resume is reflected downstream within 100 μsec. The port's Force Port Resume
bit is set to a one and the Port Change Detect bit in the USBSTS register is set to a one.
If the Port Change Interrupt Enable bit in the USBINTR register is a one the host
controller will issue a hardware interrupt.
System software observes the resume event on the port, delays a port resume time
(nominally 20 ms), then terminates the resume sequence by writing zero to the Force
Port Resume bit in the port. The host controller receives the write of zero to Force Port
Resume, terminates the resume sequence and sets Force Port Resume and Suspend
port bits to zero. Software can determine that the port is enabled (not suspended) by
sampling the PORTSC register and observing that the Suspend and Force Port Resume
bits are zero. Software must ensure that the host controller is running (i.e. HCHalted
bit in the USBSTS register is a zero), before terminating a resume by writing a zero to
a port's Force Port Resume bit. If HCHalted is a one when Force Port Resume is set to a
zero, then SOFs will not occur down the enabled port and the device will return to
suspend mode in a maximum of 10 milliseconds.
Table 170, "Behavior During Wake-Up Events" on page 418
events. Whenever a resume event is detected, the Port Change Detect bit in the
USBSTS register is set to a one. If the Port Change Interrupt Enable bit is a one in the
USBINTR register, the host controller will also generate an interrupt on the resume
event. Software acknowledges the resume event interrupt by clearing the Port Change
Detect status bit in the USBSTS register.
August 2006
Order Number: 306262--, Revision: 004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Intel
Section 9.12.11, "PORTSCx" on
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
summarizes the wake-up
Developer's Manual
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