Data Structures; Operational Model - Intel IXP45X Developer's Manual

Intel
9.15.1.4

Data Structures

The same data structures used for FS/LS transactions though a HS hub are also used
for transactions through the Root hub with sm embedded Transaction Translator. Here it
is demonstrated how the Hub Address and Endpoint Speed fields should be set for
directly attached FS/LS devices and hubs:
• QH (for direct attach FS/LS) – Async. (Bulk/Control Endpoints) Periodic (Interrupt)
— Hub Address = 0
— Transactions to direct attached device/hub.
• QH.EPS = Port Speed
— Transactions to a device downstream from direct attached FS hub.
• QH.EPS = Downstream Device Speed
Note: When QH.EPS = 01 (LS) and PORTSCx.PSPD = 00 (FS), a LS-pre-pid will be sent before
the transmitting LS traffic.
Maximum Packet Size must be less than or equal 64 or undefined behavior may result.
• siTD (for direct attach FS) – Periodic (ISO Endpoint)
— All FS ISO transactions:
• Hub Address = 0
• siTD.EPS = 00 (full speed)
Maximum Packet Size must less than or equal to 1,023 or undefined behavior may
result.
9.15.1.5

Operational Model

The operational models are well defined for the behavior of the Transaction Translator
(see USB 2.0 specification) and for the EHCI controller moving packets between system
memory and a USB-HS hub. Since the embedded Transaction Translator exists within
the host controller there is no physical bus between EHCI host controller driver and the
USB FS/LS bus. These sections will briefly discuss the operational model for how the
EHCI and Transaction Translator operational models are combined without the physical
bus between. The following sections assume the reader is familiar with both the EHCI
and USB 2.0 Transaction Translator operational models.
9.15.1.5.1 Micro-Frame Pipeline
The EHCI operational model uses the concept of H-frames and B-frames to describe the
pipeline between the Host (H) and the Bus (B). The embedded Transaction Translator
uses the same pipeline algorithms specified in the USB 2.0 specification for a hub-
based Transaction Translator.
All periodic transfers always begin at B-frame 0 (after SOF) and continue until the
stored periodic transfers are complete. As an example of the micro-frame pipeline
implemented in the embedded Transaction Translator, all periodic transfers that are
tagged in EHCI to execute in H-frame 0 will be ready to execute on the bus in B-frame
0.
It is important to note that when programming the S-mask and C-masks in the EHCI
data structures to schedule periodic transfers for the embedded Transaction Translator,
the EHCI host controller driver must follow the same rules specified in EHCI for
programming the S-mask and C-mask for downstream hub-based Transaction
Translators.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
488
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—USB 2.0 Host Controller
August 2006
Order Number: 306262-004US