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Intel 82540EP Datasheet

Intel 82540EP Datasheet

Gigabit ethernet controller
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82540EP Gigabit Ethernet Controller
Networking Silicon
Datasheet
Revision 1.2
April 2003

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Summary of Contents for Intel 82540EP

  • Page 1 82540EP Gigabit Ethernet Controller Networking Silicon Datasheet Revision 1.2 April 2003...
  • Page 2 The Intel products referenced in this document may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

  • Page 3: Revision History

    Apr 2003 Datasheet Networking Silicon — 82540EP Notes Initial Release Changed document status to Intel Confidential. Section 1.0. Replaced Block Diagram Section 2.6. Added Table footnote Section 4.1, 4.2, 4.3. Replaced tables Section 5.1. Added Visual Pin Reference Section 4.4 Removed Power Supply Characteristics; added note to I/O Charac- teristics Section 5.0 Replaced Pinout Diagram...
  • Page 4 82540EP — Networking Silicon Note: This page is intentionally left blank. Datasheet...

  • Page 5: Table Of Contents

    Contents Introduction... 1 Document Scope ...3 Reference Documents... 3 Product Code ... 3 Features of the 82540EP Gigabit Ethernet Controller... 5 PCI Features ... 5 MAC Specific Features... 5 PHY Specific Features ... 6 Host Offloading Features ... 6 Manageability Features ... 7 Additional Device Features ...
  • Page 6 82540EP — Networking Silicon 4.5.3 EEPROM Interface... 26 Package and Pinout Information ... 27 Device Identification ... 27 Package Information ... 28 Thermal Specifications ... 29 Pinout Information ... 30 Visual Pin Reference... 39 Datasheet...

  • Page 7: Introduction

    PCI bus traffic and a PCI interface that maximizes the use of bursts for efficient bus usage. The 82540EP caches up to 64 packet descriptors in a single burst for efficient PCI bandwidth use. A large 64 KByte on-chip packet buffer maintains superior performance as available PCI bandwidth changes.
  • Page 8 82540EP — Networking Silicon Figure 1. Gigabit Ethernet Controller Block Diagram Data Alignment Packet Buffer Interface CSR Register Access TX Data Datasheet...

  • Page 9: Document Scope

    Document Scope This document contains datasheet specifications for the 82540EP Gigabit Ethernet Controller, including signal descriptions, DC and AC parameters, packaging data, and pinout information. Reference Documents This application assumes that the designer is acquainted with high-speed design and board layout techniques.
  • Page 10 82540EP — Networking Silicon Note: This page is intentionally left blank. Datasheet...

  • Page 11: Features Of The 82540Ep Gigabit Ethernet Controller

    Features of the 82540EP Gigabit Ethernet Controller PCI Features PCI Revision 2.3 support for 32-bit wide interface at 33 MHz and 66 MHz Algorithms that optimally use advanced PCI, MWI, MRM, and MRL commands CardBus Information Services (CIS) Pointer CLKRUN# Signal...

  • Page 12: Phy Specific Features

    82540EP — Networking Silicon PHY Specific Features Integrated PHY for 10/100/1000 Mbps full and half duplex operation IEEE 802.3ab Auto-Negotiation support IEEE 802.3ab PHY compliance and compatibility State-of-the-art DSP architecture implements digital adaptive equalization, echo cancellation, and cross- talk cancellation...

  • Page 13: Manageability Features

    Easy system monitoring with industry standard consoles • Remote network management capabilities through DMI 2.0 and SNMP software • Packet recognition and wake-up for NIC and LOM applications without software configuration • Assures link under adverse cable configurations Networking Silicon — 82540EP Benefits...

  • Page 14: Additional Device Features

    Two or three-pair cable downshift Provides loopback capabilities Minimal ballout change from the 82540EM a. If applying the “low-power” EEPROM setting for the 82540EP chip, then only external voltage regulator circuits should be used instead of the on-chip power control circuitry Technology Features...

  • Page 15: Signal Descriptions

    Analog. PHY analog data signal. Power. Power connection, voltage reference, or other reference connection. PCI Bus Interface When the Reset signal (RST#) is asserted, the 82540EP will not drive any PCI output or bi- directional pins except the Power Management Event signal (PME#). 3.2.1...
  • Page 16 When the 82540EP controller is a bus master, it drives PAR for address and write data phases, and as a slave device, drives PAR for read data phases.

  • Page 17: Arbitration Signals

    The 82540EP device does not implement bus locking. Name and Function Interrupt A. Interrupt A is used to request an interrupt by port 1 of the 82540EP. It is an active low, level-triggered interrupt signal. Name and Function PCI Clock.

  • Page 18: Power Management Signals

    Name and Function Power Good (Power-on Reset). The Power Good signal is used to indicate that stable power is available for the 82540EP. When the signal is low, the 82540EP holds itself in reset state and floats all PCI signals.

  • Page 19: Miscellaneous Signals

    EEPROM. The upper four bits may be mapped to the General Purpose Interrupt bits if they are configured as input signals. Note: SDP5 is not included in the group of Software Defined Pins. Networking Silicon — 82540EP...

  • Page 20: Phy Signals

    82540EP — Networking Silicon P H Y S i g n a l s 3.5.1 Crystal Signals Symbol Type XTAL1 XTAL2 3.5.2 Analog Signals Symbol Type MDI[0]+/- MDI[1]+/- MDI[2]+/- MDI[3]+/- Name and Function Crystal One. The Crystal One pin is a 25 MHz +/- 50 ppm input signal. It can be connected to either an oscillator or crystal.

  • Page 21: Test Interface Signals

    Clock View. Output for GTX_CLK and RX_CLK during IEEE PHY conformance testing. The clock is selected by register programming. Name and Function 3.3 V I/O Power Supply. 1.5 V Digital Core Power Supply. Name and Function 3.3 V Analog Power Supply. 2.5 V Analog Power Supply. Networking Silicon — 82540EP...

  • Page 22: Ground And No Connects

    82540EP — Networking Silicon 3.7.3 Ground and No Connects Symbol Type 3.7.4 Control Signals Symbol Type CTRL_15 CTRL_25 Name and Function Ground. No Connect. Do not connect any circuitry to these pins. Pull-up or pull-down resistors should not be connected to these pins.

  • Page 23: Voltage, Temperature, And Timing Specifications

    Voltage, Temperature, and Timing Specifications Note: The specification values listed in this section are subject to change without notice. Verify with your local Intel sales office that you have the latest information before finalizing a design. Absolute Maximum Ratings Table 1.

  • Page 24: Dc Specifications

    82540EP — Networking Silicon Table 2. Recommended Operating Conditions Symbol Parameter Analog High VDD Range Core Digital Voltage Range Analog Low VDD Range a. Sustained operation of the device at conditions exceeding these values, even if they are within the absolute maximum rating limits, might result in permanent damage.
  • Page 25 @100Mbps Typ Icc Max Icc Typ Icc Max Icc (mA) (mA) (mA) (mA) Networking Silicon — 82540EP D3cold - wake D3cold - wake disabled - max disabled - max power savings power savings mode disabled mode enabled Typ Icc...
  • Page 26 82540EP — Networking Silicon Table 7. Power Specifications - Complete Subsystem 2.5V 1.5V Subsystem 70 mA 3.3V current Table 8. I/O Characteristics Symbol Voltage input LOW Voltage input HIGH Voltage output LOW Voltage output HIGH Schmitt Trigger Hysterysis Output current LOW...

  • Page 27: Ac Characteristics

    Table 12. EEPROM Interface Clock Requirements Symbol Table 13. AC Test Loads for General Output Pins Symbol PME#, SDP[7:0] EE_DI, EE_SK RX_ACTIVITY, TX_ACTIVITY, LINK_UP Datasheet Networking Silicon — 82540EP Parameter Parameter 25 - 50 ppm Parameter Parameter Signal Name Unit...

  • Page 28: Timing Specifications

    82540EP — Networking Silicon Figure 1. AC Test Loads for General Output Pins Timing Specifications Note: Timing specifications are subject to change. Verify with your local Intel sales office that you have the latest information before finalizing a design. 4.5.1 PCI Bus Interface 4.5.1.1...
  • Page 29 3. Input timing measurements are as shown. Figure 3. PCI Bus Interface Output Timing Measurement PCI_CLK Output Delay Tri-State Output Datasheet PCI 66MHz Parameter TCYC TEST output current leakage current Networking Silicon — 82540EP PCI 33 MHz Units 10, 12 TCYC TEST (3.3V Signalling) STEP...
  • Page 30 82540EP — Networking Silicon Figure 4. PCI Bus Interface Input Timing Measurement Conditions PCI_CLK Input Table 16. PCI Bus Interface Timing Measurement Conditions Symbol Input measurement test voltage (high) Input measurement test voltage (low) VTEST Output measurement test voltage Input signal slew rate Figure 5.
  • Page 31 N o t e : 5 0 p F l o a d u s e d f o r m a x i m u m t i m e s . M i n i m u m t i m e s a r e s p e c i f i e d w i t h 0 p F l o a d . Datasheet Networking Silicon — 82540EP 1/2 inch max.

  • Page 32: Link Interface Timing

    82540EP — Networking Silicon 4.5.2 Link Interface Timing Table 17. Rise and Fall Times Symbol Parameter Clock rise time Clock fall time Data rise time Data fall time Figure 9. Link Interface Rise/Fall Timing 4.5.3 EEPROM Interface Table 18. Link Interface Clock Requirements...

  • Page 33: Package And Pinout Information

    Package and Pinout Information This section describes the 82540EP device, manufactured in a 196-lead ball grid array measuring 15mm X 15mm. External product identification is shown in 1mm. The pin number-to-signal mapping is indicated beginning with Device Identification Figure 10. 82540EP Device Identification Markings RC82540EP YYWW ©...

  • Page 34: Package Information

    82540EP — Networking Silicon Package Information The 82540EP device is a 196-lead ball grid array (TFBGA) measuring 15 mm dimensions are detailed in Figure 11. 82540EP Mechanical Specifications Figure 11. The nominal ball pitch is 1 mm. . The package...

  • Page 35: Thermal Specifications

    Thermal Specifications The 82540EP device is specified for operation when the ambient temperature (TA) is within the ° ° range of 0 C to 70 TC (case temperature) is calculated using the equation: TC = TA + P ( JA - q JC)

  • Page 36: Pinout Information

    82540EP — Networking Silicon Pinout Information Table 19. PCI Address, Data, and Control Signals Signal PCI_AD[0] PCI_AD[1] PCI_AD[2] PCI_AD[3] PCI_AD[4] PCI_AD[5] PCI_AD[6] PCI_AD[7] PCI_AD[8] PCI_AD[9] PCI_AD[10] PCI_AD[11] PCI_AD[12] PCI_AD[13] PCI_AD[14] PCI_AD[15] Table 20. PCI Arbitration Signals Signal REQ# GNT# Table 21. Interrupt Signals...
  • Page 37 Table 30. IEEE Test Signals Signal CLK_VIEW Datasheet Signal AUX_PWR CLKRUN# Signal ZP_COMP Signal SMBDATA Signal EE_DI FL_CE# FL_SI Signal LED2 / LINK100# LED3 / LINK1000# Signal SDP6 SDP7 Networking Silicon — 82540EP Signal SMBALRT# Signal FL_SCK FLSO Signal CTRL_15 CTRL_25...
  • Page 38 82540EP — Networking Silicon Table 31. PHY Signals Signal XTAL1 XTAL2 MDI0- Table 32. Test Interface Signals Signal JTAG_TCK JTAG_TDI Table 33. Digital Power Signals Signal DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V)
  • Page 39 Table 36. Signal Names in Pin Order (Sheet 1 of 6) Signal Name SERR# VDDO (3.3V) IDSEL PCI_AD[25] PME# VDDO (3.3V) PCI_AD[30] LAN_PWR_GOOD SMBCLK VDDO (3.3V) LED0 / LINK# TEST PCI_AD[22] PCI_AD[23] PCI_AD[24] Datasheet Signal Signal Networking Silicon — 82540EP Signal...
  • Page 40 82540EP — Networking Silicon Table 36. Signal Names in Pin Order (Sheet 2 of 6) (Continued) Signal Name PCI_AD[26] PCI_AD[27] PCI_AD[31] RST# SMBALRT# LED2 / LINK100# LED3 / LINK1000# CTRL_25 PCI_AD[21] M66EN REQ# CBE3# PCI_AD[28] PCI_AD[29] CLKRUN# SMBDATA LED1 / ACT#...
  • Page 41 Table 36. Signal Names in Pin Order (Sheet 3 of 6) (Continued) Signal Name VDDO (3.3V) PCI_AD[17] DVDD (1.5V) DVDD (1.5V) MDI1+ MDI1- IRDY# FRAME# CBE2# MDI2+ MDI2- TRDY# ZP_COMP DVDD (1.5V) DVDD (1.5V) Datasheet Networking Silicon — 82540EP...
  • Page 42 82540EP — Networking Silicon Table 36. Signal Names in Pin Order (Sheet 4 of 6) (Continued) Signal Name AVDDL (2.5 V) DVDD (1.5V) STOP# INTA# DEVSEL# ZN_COMP DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) DVDD (1.5V) MDI3+ MDI3- PERR# GNT# DVDD (1.5V)
  • Page 43 DVDD (1.5V) VDDO (3.3V) XTAL1 PCI_AD[14] PCI_AD[15] CBE1# DVDD (1.5V) DVDD (1.5V) AVDDL (2.5 V) DVDD (1.5V) DVDD (1.5V) JTAG_TMS JTAG_RST# JTAG_TCK PCI_AD[11] PCI_AD[12] PCI_AD[13] CBE0# PCI_AD[5] PCI_AD[1] CLK_VIEW FL_CE# EE_SK FL_SI SDP7 JTAG_TDI JTAG_TDO PCI_AD[10] Datasheet Networking Silicon — 82540EP...
  • Page 44 82540EP — Networking Silicon Table 36. Signal Names in Pin Order (Sheet 6 of 6) (Continued) Signal Name PCI_AD[9] PCI_AD[7] PCI_AD[4] VDDO (3.3V) PCI_AD[0] VDDO (3.3V) FL_SCK EE_DO SDP6 SDP0 VDDO (3.3V) PCI_AD[8] PCI_AD[6] PCI_AD[3] PCI_AD[2] EE_CS FL_SO EE_DI CTRL_15 VDDO (3.3V)

  • Page 45: Visual Pin Reference

    1.5V 1.5V 1.5V 1.5V 1.5V PCIZP PCIZN CBE# AD17 TRDY# GNT# SEL# FRAME INTA# PERR# 3.3V IRDY# STOP# Networking Silicon — 82540EP JTCK JTDO SDP[0] 3.3V JTRST# JTDI SDP[6] SDP[1] JTMS SDP[7] 3.3V FLSH CTRL 1.5V 1.5V 1.5V EESK EEDO...

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