Ecc Write Flow; Ecc Generation - Intel IXP45X Developer's Manual

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Memory Controller—Intel
11.2.3.1

ECC Generation

For write operations, the MCU generates the error correction code which is written
along with the data. This section describes the operation of the DDRI SDRAM Control
Block for ECC generation in a 64-bit wide memory and 64-bit region. The same
principles apply for 32-bit wide memory, though the MCU will generate 8-bit wide ECC
by zero extending the data to 64-bits.
The algorithm for a write transaction is:
if data to write is 64/32 bits wide
Generate the ECC_with the G-matrix
Write the new data and ECC
else {Partial Write}
Read entire 64/32-bit data word from memory
Merge the new data portion with the data from memory
Generate the new ECC with the G-matrix
Write new data and ECC
Figure 118
transaction.
Figure 118. ECC Write Flow
August 2006
Order Number: 306262-004US
®
IXP45X and Intel IXP46X Product Line of Network Processors
shows how the data logically flows through the ECC hardware for a write
Main
Memory
MCU
Data from Internal Bus
ECC
Memory
Calculate ECC
with G-matrix
32-bit Zero-extend (0x00000000)
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
B2450-01
Developer's Manual
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