Random Number Fifo; Power-Management Requirements - Intel IXP45X Developer's Manual

24.2.1 Registers
24.2.1.1

Random Number FIFO

Register Name:
Block
0x7000
Base Address:
FIFO containing random numbers generated by the RNG. After a
number is read, it is removed from the stack, and the next number
Register Description:
is made available
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
Random
31:0 Number at top of random number FIFO stack.
Number
24.3

Power-Management Requirements

The RNG implements no power management features.
24.4 Reset
On Power-On reset, all internal flip-flops — with the exception of the random-number
FIFO — are initialized. The pointers to the random number FIFO are, however,
initialized, effectively "emptying" the random number FIFO.
After reset clears, the unit initializes itself prior to beginning to fill the random number
FIFO. No read request will be fulfilled until at least one word has been loaded into the
random number FIFO.
24.5 Error/Abnormal Conditions
In the event of a FIFO underflow, the RNG will not assert the
preventing the completion of a read operation, until a new word is available. This may
result in longer access times under certain operational conditions.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
912
® ®
Intel IXP45X and Intel
Offset Address
RNG_FIFO
Description
IXP46X Product Line of Network Processors—Random Number
RNG_FIFO
_2100
RNG_FIFO
Generator
Unknown
Reset Value
Access: (See below.)
8 7 6 5 4 3 2 1
Reset
Access
Value
Unknown
signal, thus
rng_rdy
August 2006
Order Number: 306262-004US
0
RO