Instruction-Cache Coherence - Intel IXP45X Developer's Manual

Intel
Example 4. Recovering from an Instruction Cache Parity Error
; Prefetch abort handler
MCR P15,0,R0,C7,C5,0
CPWAIT
for a
SUBS PC,R14,#4
; The Instruction Cache is guaranteed to be invalidated at this point
If a parity error occurs on an instruction that is locked in the cache, the software
exception handler needs to unlock the instruction cache, invalidate the cache and then
re-lock the code in before it returns to the faulting instruction.
The instruction cache does not detect modification to program memory by loads, stores
or actions of other bus masters. Several situations may require program memory
modification, such as uploading code from disk.
The application program is responsible for synchronizing code modification and
invalidating the cache. In general, software must ensure that modified code space is
not accessed until modification and invalidating are completed.
3.2.1.3

Instruction-Cache Coherence

To achieve cache coherence, instruction cache contents can be invalidated after code
modification in external memory is complete.
If the instruction cache is not enabled, or code is being written to a non-cacheable
region, software must still invalidate the instruction cache before using the newly-
written code. This precaution ensures that state associated with the new code is not
buffered elsewhere in the processor, such as the fetch buffers or the BTB.
Naturally, when writing code as data, care must be taken to force it completely out of
the processor into external memory before attempting to execute it. If writing into a
non-cacheable region, flushing the write buffers is sufficient precaution (see
7: Cache Functions" on page 103
cacheable region, then the data cache should be submitted to a Clean/Invalidate
operation (see
After reset, the instruction cache is always disabled, unlocked, and invalidated
(flushed).
The instruction cache is enabled by setting bit 12 in coprocessor 15, register 1 (Control
Register). This process is illustrated in
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IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
; Invalidate the instruction cache and branch target
; buffer
; wait for effect (see
; description of CPWAIT)
; Returns to the instruction that generated the
; parity error
"Cacheability" on page
"Additions to CP15 Functionality" on page 176
for a description of this operation). If writing to a
88) to ensure coherency.
Example 5, Enabling the Instruction
®
Processor
"Register
Cache.
August 2006
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