Texas Instruments* Synchronous Serial Frame Format; Ssp Format — Detail; Spi Format — Detail - Intel IXP45X Developer's Manual

Synchronous Serial Port—Intel
20.2.1.1 SSP Format — Detail
When outgoing data in the SSP controller is ready to transmit, SSP_SFRM asserts for
one clock period. On the following clock, data to be transmitted is driven on SSP_TXD
one bit at a time, most significant bit first. Similarly, the peripheral drives data on the
SSP_RXD pin. Word length may be from 4 to 16 bits. All transitions take place on the
rising edge of SSP_SCLK and data sampling is done on the falling edge. At the end of
the transfer, SSP_TXD retains the value of the last bit sent (bit 0) through the next idle
period. If the SSP Port is disabled or reset, SSP_TXD is forced to zero.
Table 270
transmitted frame and when back-to-back frames are transmitted. Once the bottom
entry of the transmit FIFO contains data, SSP_SFRM is pulsed high for one SSP_SCLK
period and the value to be transmitted is transferred from the transmit FIFO to the
transmit logic's serial shift register. On the next rising edge of SSP_SCLK, the MSB of
the 4 to 16-bit data frame is shifted to the SSP_TXD pin. Likewise, the MSB of the
received data is shifted onto the SSP_RXD pin by the off-chip serial slave device. Both
the SSP and the off-chip serial slave device then latch each data bit into their serial
shifter on the falling edge of each SSP_SCLK. The received data is transferred from
the serial shifter to the receive FIFO on the first rising edge of SSP_SCLK after the LSB
has been latched.
.
Table 270. Texas Instruments
SSP_S
CLK
SSP_S
FRM
SSP_T
XD
SSP_R
XD
SSP_S
CLK
SSP_S
FRM
TX/RX
20.2.1.2 SPI Format — Detail
Note that there are four possible sub-modes of the SPI format depending on the
SSP_SCLK edges selected for driving data and sampling received data, and on the
selection of the phase mode of SSP_SCLK see
page 866
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
shows the Texas Instruments synchronous serial frame format for a single
*
Synchronous Serial Frame Format
Bit<N>
Bit<N>
MSB
Bit<N-
Bit<0> Bit<N>
1>
for complete description of each mode).
...
...
Bit<N-
... Bit<1> Bit<0>
1>
Bit<N-
... Bit<1> Bit<0>
1>
4 to 16 Bits LSB
Single Transfer
...
...
... Bit<1> Bit<0> Bit<N>
Continuous Transfers
"SSP Control Register 1 (SSCR1)" on
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
...
...
Bit<N-
... Bit<1> Bit<0>
1>
Developer's Manual
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