Internal Bus; North Ahb - Intel IXP45X Developer's Manual

Functional Overview—Intel
• HSS Serialization/ De-serialization
• DES/3DES/AES
• MD-5
• Learning/filtering content
addressable memory
• UTOPIA Level 2 Framing
These coprocessors are implemented in hardware, enabling the coprocessors and the
NPE processor core to operate in parallel.
With the addition of the new switching coprocessor (SWCP) and the Ethernet
coprocessors, functions like a four-port, Layer-2 switch can be easily implemented
using all Intel-based silicon. Also, by using NPEs to implement switching functions,
value added features like VLAN or IP switching can be easily upgraded using existing
silicon.
The combined forces of the hardware multi-threading, independent instruction
memory, independent data memory, and parallel processing — contained on the NPE —
allows the Intel XScale processor to be utilized for application purposes. The multi-
processing capability of the peripheral interface functions allows unparalleled
performance to be achieved by the application running on the Intel XScale processor.
Note: All the described NPE functions require Intel-supplied software executing on the NPEs.
For further information, see the Intel
information on the availability of the NPE software and its enabling functions, contact
your local sales representative.
2.1.2

Internal Bus

The internal bus architecture of the IXP45X/IXP46X network processors are designed to
allow parallel processing to occur and to isolate bus utilization, based on particular
traffic patterns. The bus is segmented into four major buses:
• North - Advanced High Performance Bus
(AHB)
• South - AHB
2.1.2.1

North AHB

The North AHB is a 133.32-MHz, 32-bit bus that can be mastered by the NPE A, NPE B,
or NPE C. The targets of the North AHB can be the DDRI memory controller or the AHB/
AHB bridge. The AHB/AHB bridge allows the NPEs to access the peripherals and internal
targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted
predominately to the queue manager. Transfers to the AHB/AHB bridge may be
"posted" when writing or "split" when reading.
When a transaction is "posted," a master on the North AHB requests a write to a
peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write
request will be transferred from the master on the North AHB to the AHB/AHB bridge.
August 2006
Reference Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
• CRC checking/generation
• SHA-1/256/384/512
• HDLC bit stuffing/de-stuffing
• Media Access Controller functionality
• DMA capability of data movement to
and from DDRI memory
®
IXP400 Software Programmer's Guide. For
• Memory Port Interface
• Advanced Peripheral Bus
(APB)
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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