Memory Controller - Intel IXP45X Developer's Manual

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Memory Controller—Intel
11.0

Memory Controller

This chapter describes the integrated Memory Controller Unit (DDRI MCU) of the Intel
IXP45X and Intel
initialization, external interfaces, and implementation are detailed in this chapter.
11.1 Overview
The IXP45X/IXP46X network processors integrate a high performance, multi-ported
Memory Controller to provide a direct interface between the processor and its local
memory subsystem. The Memory Controller supports:
• 128/256/512-Mbit, 1-Gbit DDRI SDRAM technology support.
• Unbuffered DRAM support only, no registered DRAM support.
• Dedicated port for Intel XScale
first reads).
• Between 32 Mbytes and 1 Gbytes of 32-bit DDRI SDRAM for low cost solutions.
• Two AHB ports for access from units other than Intel XScale processor (no critical
word first support).
• All MMR accesses must go through the South AHB port.
• Single-bit error correction, multi-bit detection support (ECC).
• 32-, 40- wide Memory Interfaces (non-ECC and ECC support).
The DDRI SDRAM interface provides a direct connection to a reliable, high bandwidth
memory subsystem. The DDRI SDRAM interface consists of a 32-bit wide data path to
support up to 1066 Mbytes/sec. throughput. An 8-bit Error Correction Code (ECC)
across each 32-bit word improves system reliability. The ECC is stored into the DDRI
SDRAM array along with the data and is checked when the data is read. If the code is
incorrect, the MCU corrects the data (if possible) before reaching the initiator of the
read. User-defined fault correction software is responsible for scrubbing the memory
array.
The MCU supports two physical banks of DDRI SDRAM in the form of discrete chips.
— The MCU only supports Unbuffered DDRI memory types.
• The MCU supports a 32-bit DDRI SDRAM data interface.
• The MCU contains transaction queues for each port enabling pipelining of
transactions to the DDRI SDRAM for maximum performance.
• The MCU provides two chip enables to the memory subsystem. These two chip
enables service the DDRI SDRAM subsystem (one per bank).
• Performance monitors for page hit / miss and read latency per port.
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
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IXP46X Product Line of Network Processors. The operating modes,
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Processor to DDRI SDRAM (Supports critical word
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
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Developer's Manual
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