Additions To Cp15 Functionality; Second-Level Descriptors For Fine - Intel IXP45X Developer's Manual

Intel
Table 74. Second-Level Descriptors for Fine Page Table
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
The TEX (Type Extension) field is present in several of the descriptor types. In the Intel
XScale processor, only the LSB of this field is defined; this is called the X bit. The
remaining bits are reserved for future use and should be programmed as zero (SBZ) on
the IXP45X/IXP46X network processors.
A Small Page descriptor does not have a TEX field. For these descriptors, TEX is
implicitly zero; that is, they operate as if the X bit had a '0' value.
The X bit, when set, modifies the meaning of the C and B bits. Description of page
attributes and their encoding can be found in
3.8.3.3

Additions to CP15 Functionality

To accommodate the functionality in the Intel XScale processor, registers in CP15 and
CP14 have been added or augmented. See
At times it is necessary to be able to guarantee exactly when a CP15 update takes
effect. For example, when enabling memory address translation (turning on the MMU),
it is vital to know when the MMU is actually guaranteed to be in operation. To address
this need, a processor-specific code sequence is defined for the Intel XScale processor.
The sequence — called CPWAIT — is shown in
Example 17. CPWAIT: Canonical Method to Wait for CP15 Update
;; The following macro should be used when software needs to be
;; assured that a CP15 update has taken effect.
;; It may only be used while in a privileged mode, because it
;; accesses CP15.
MACRO CPWAIT
ENDM
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
176
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Large page base address
Small page base address
Tiny Page Base Address
MRC P15, 0, R0, C2, C0, 0
MOV R0, R0
SUB PC, PC, #4
; At this point, any previous CP15 writes are
; guaranteed to have taken effect.
SBZ
TEX AP3 AP2
AP3 AP2
"Memory Management Unit" on page
"Configuration" on page 96
Example 12 on page
; arbitrary read of CP15
; wait for it
; branch to next instruction
®
Processor
8 7 6 5 4 3 2 1
0
AP1 AP0 C B 0
AP1 AP0 C B 1
TEX AP C B 1
69.
for details.
108.
August 2006
Order Number: 306262-004US
0
0
1
0
1