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Figure 34
assumptions are made for the figure:
• There are eight active physical interfaces connected named A through H which map
to logical address 0 through 7.
• Physical Interface A is the currently selected physical interface for clock cycles 0
through18.
• Notice on clock 7 that the result from Physical Interface G is that Physical Interface
G has a full cell ready for the IXP45X/IXP46X network processors. The UTP_IP_FCI
signal flags that a full cell is ready to be sent by Physical Interface G to the IXP45X/
IXP46X network processors, asserting the UTP_IP_FCI to logic 1 one clock after
Physical Interface G has been polled.
• On clock 16, the final Physical Interface polled is the Physical Interface that is
currently selected. This polling is irrelevant to the Physical Interface that was polled
previously prior to this location.
• Notice on clock cycles 18 and 19 that Physical Interface G is selected as the next
Physical Interface that the IXP45X/IXP46X network processors will receive data
from that Physical Interface.
Figure 34.
UTOPIA Level 2 MPHY Receive Polling
0
UTP_IP_CLK
UTP_IP_ADDR (4:0)
D
UTP_IP_FCI
(a.k .a. -RX _CLAV )
UTP_IP_FCO
(a.k .a. -RX _ENB_N )
35
UTP_IP_DATA (7:0)
UTP_IP_SOC
In cell-level single-PHY (SPHY) mode, the physical interface indicates that a cell is
ready to be sent by asserting the UTP_IP_FCI (a.k.a. RX_EMPTY_N/RX_CLAV) signal.
The UTOPIA Level-2 Interface on the IXP45X/IXP46X network processors subsequently
initiates the transfer of a cell from the physical interface by asserting UTP_IP_FCO
(a.k.a. RX_ENB_N).
In octet-level single-PHY (SPHY) mode, the UTOPIA Level 2 Interface on the IXP45X/
IXP46X network processors indicates to the physical interface that the UTOPIA Receive
interface is ready to receive bytes by asserting UTP_IP_FCO (a.k.a. RX_ENB_N) signal.
The physical interface indicates a valid byte is on the UTOPIA data bus by de-asserting
UTP_IP_FCI (also known as RX_EMPTY_N/RX_CLAV) signal.
The Receive Module maintains various statistical counters. The statistics that can be
maintained are on a single physical port address on a specified VPI/VCI address value.
The 32-bit counters will maintain the following counts:
• The number of cells received
• The number of cells with an incorrect cell size
• The number of cells containing HEC errors.
• The number of idle cells received
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
274
®
Intel
IXP45X and Intel
shows the reception of a cell in multiple-PHY (MPHY) mode. The following
1
2
3
4
5
6
7
8
H
E
F
G
36
37
38
39 40
41
42
43
®
IXP46X Product Line of Network Processors—UTOPIA Level 2
9
10 11
12
13
14
15
16
A
B
C
A
44
45
46
47
48
49
50 51
17
18
19
20
21
22
23
24
G
D
E
F
52
53
1
2
3
4
5
B4326 -02
Reference Number: 306262-004US
25
26
G
7
6
August 2006
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