Ldic Jtag Data Register; Ldic Jtag Data Register Hardware - Intel IXP45X Developer's Manual

Intel
3.6.14.2

LDIC JTAG Data Register

The LDIC JTAG Data Register is selected when the LDIC JTAG instruction is in the JTAG
IR. An external host can load and invalidate lines in the instruction cache through this
data register.
Figure 22.

LDIC JTAG Data Register Hardware

TDI
LDIC_SR1
LDIC_REG
LDIC_SR2
The data loaded into LDIC_SR1 during a Capture_DR is unpredictable.
All LDIC functions and data consists of 33-bit packets which are scanned into LDIC_SR1
during the Shift_DR state.
Update_DR parallel loads LDIC_SR1 into LDIC_REG which is then synchronized with the
IXP45X/IXP46X network processors' clock and loaded into the LDIC_SR2. Once data is
loaded into LDIC_SR2, the LDIC State Machine turns on and serially shifts the contents
if LDIC_SR2 to the instruction cache.
Note that there is a delay from the time of the Update_DR to the time the entire
contents of LDIC_SR2 have been shifted to the instruction cache. Removing the LDIC
JTAG instruction from the JTAG IR before the entire contents of LDIC_SR2 are sent to
the instruction cache, will result in unpredictable behavior. Therefore, following the
Update_DR for the last LDIC packet, the LDIC instruction must remain in the JTAG IR
for a minimum of 15 TCKs. This ensures the last packet is correctly sent to the
instruction cache.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
140
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
unpredictable
32
32
32
LDIC
State Machine
Capture_DR
TDO
3 2 1 0
Update_DR
2 1 0
2 1 0
To Instruction Cache
®
Processor
TCK
Core CLK
B4348-01
August 2006
Order Number: 306262-004US