Udc Frame Number Low Register - Intel IXP45X Developer's Manual

Register Name:
0 x C800B060
Hex Offset Address:
Register
Universal Serial Bus Device Frame Number High Register
Description:
Access: Read-Only
31
Bits
31:8
7
6
5
4
3
2:0
8.5.23

UDC Frame Number Low Register

The UDC frame number low register is the eight least-significant bits of the 11-bit
frame number contained in the last received SOF packet. The three remaining bits are
located in the UFNHR. This information is used for isochronous transfers.
These bits are updated every SOF.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
336
® ®
Intel IXP45X and Intel
(Reserved)
X
Resets (Above)
Register
Name
Reserved for future use.
SOF Interrupt Request (read/write 1 to clear).
SIR
1 = SOF has been received.
SOF interrupt mask.
SIM 0 = SOF interrupt enabled.
1 = SOF interrupt disabled.
Isochronous Packet Error Endpoint 14 (read/write 1 to clear).
IPE14
1 = Status indicator that data in the endpoint fifo is corrupted.
Isochronous Packet Error Endpoint 9 (read/write 1 to clear).
IPE9
1 = Status indicator that data in the endpoint fifo is corrupted.
Isochronous Packet Error Endpoint 4 (read/write 1 to clear).
IPE4
1 = Status indicator that data in the endpoint fifo is corrupted.
Frame Number MSB.
FNMSB
Most-significant three bits of 11-bit frame number associated with last receive
SOF. Reset to all zeros.
IXP46X Product Line of Network Processors—USB 1.1 Device
UFNHR
0x00000040
Reset Hex Value:
Bits
UFNHR
Description
Controller
8 7 6 5 4 3 2 1
0 1 0 0 0 0 0
(UFNLR)
August 2006
Order Number: 306262-004US
0
0