Multiple Ixp45X/Ixp46X Network Processors Connected Back-To-Back - Intel IXP45X Developer's Manual

Expansion Bus Controller—Intel
Processors
Figure 149. Multiple IXP45X/IXP46X network processors Connected Back-to-Back
Notes:
1. The IXP45X/IXP46X network processors cannot perform an outbound burst transfer to another processor, thus the
ex_burst pin for processor-to-processor transfers must be low. If there are no other masters on the exp bus besides the
two IXP45X/IXP46X network processors, it is not necessary to tie an address bit to ex_burst. In this case, ex_burst can
be tied to vss. If there are other masters on the exp bus, tie an address pin that will always be zero to ex_burst.
2. Board pull-ups exist for these pins (ex_rdy_n may have pull-downs dependent on the programmed polarity of these
pins). For ex_cs_n, all bits have board pull-ups. CS 1 and 2 are arbitrary. Each of the IXP45X/IXP46X network processors
can be on any CS (although not the same CS) except for CS 0, which is flash used for boot.
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel
EX_ALE
EX_ADDR[24:0]
EX_BE_N[3:0]
EX_CLK
EX_CS_N[7:0] *** B (EX_CS_N[2])
EX_DATA[31:0]
EX_GNT_REQ_N D
EX_GNT_N[3:1]
F
EX_IOWAIT_N
C (EX_CS_N[1])
EX_SLAVE_CS_N
EX_PARITY[3:0]
EX_RD_N
EX_RDY_N[3:0] ***
E
EX_REQ_GNT_N
EX_REQ_N[3:1] ***
A
EX_BURST *
G
EX_WAIT_N
EX_WR_N
IXP46X Product Line of Network
A EX_ADDR[23] *
External Clk source
C (EX_CS_N[1])
E
G
B (EX_CS_N[2])
D
A
F
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
EX_ALE
EX_ADDR[24:0]
EX_BE_N[3:0]
EX_CLK
EX_CS_N[7:0] ***
EX_DATA[31:0]
EX_GNT_REQ_N
EX_GNT_N[3:1]
EX_IOWAIT_N
EX_SLAVE_CS_N
EX_PARITY[3:0]
EX_RD_N
EX_RDY_N[3:0] ***
EX_REQ_GNT_N
EX_REQ_N[3:1] ***
EX_BURST *
EX_WAIT_N
EX_WR_N
B4437-02
Developer's Manual
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