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12.5.12
EXP_SMIIDLL
Register Name:
Physical Address:
Register Description:
Access: See below.
3
1
Register
Bits
Name
31:1
(Reserved)
(Reserved)
0
9:0
exp_smiidll
This field must be programmed to 0x18E before enabling SMII mode.
12.5.13
EXP_MST_CONTROL
Register Name:
Physical Address:
Register Description:
Access: See below.
3
1
Register
Bits
Name
31:5
(Reserved)
Reserved
Allows External Masters to write EXP_INBOUND_ADDR register
4
ExtCfg
0 = External master writes to EXP_INBOUND_ADDR are enabled
1 = External master writes to EXP_INBOUND_ADDR are ignored
Odd or even parity is generated/compared on EX_PARITY for Inbound
and Outbound accesses.
3
OddPar
0 = Even parity on EX_PARITY
1 = Odd parity on EX_PARITY
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
716
®
®
Intel
IXP45X and Intel
0xC400002C
DLL bits for SMII used by the SMII DLL.
(Reserved)
Description
0xC4000100
Specifies values for bus arbitration priority, bus master locking, and external master
parity support
(Reserved)
Description
IXP46X Product Line of Network Processors—Expansion Bus
EXP_SMIIDLL
Reset Hex Value:
1
9
0
EXP_SMIIDLL
EXP_MST_CONTROL
Reset Hex Value:
EXP_MST_CONTROL
Controller
0x00000000
0
exp_smiidll
Reset
Access
Value
0x0
RO
0x0
RW
0x00000000
5
4
3
2
1
0
Reset
Access
Value
0x0
RO
0
RW
0
RW
August 2006
Order Number: 306262-004US
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