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82543GC
Intel 82543GC Manuals
Manuals and User Guides for Intel 82543GC. We have
1
Intel 82543GC manual available for free PDF download: Specification Update
Intel 82543GC Specification Update (24 pages)
Gigabit Ethernet Controller
Brand:
Intel
| Category:
Network Hardware
| Size: 0.12 MB
Table of Contents
Contents
3
Table of Contents
3
Gc Gigabit Ethernet Controller Specification Update
5
Revision History
5
Preface
7
Nomenclature
7
Component Identification Via Programming Interface
7
General Information
8
82543GC Component Marking Information
8
Summary Table of Changes
9
Codes Used in Summary Tables
9
Specification Changes
11
GMII Setup and Hold Times
11
Errata
11
MDI Control Register Returns Incorrect Values
11
Descriptor Queue Maximum Size Limitation
11
Late Collision Statistics May be Incorrect
11
Some Registers Cannot be Accessed During Reset
12
DAC Accesses May be Interpreted Incorrectly
12
Flash Memory Interface Functions Incorrectly in 64-Bit Address Space
12
Excessive Errors in 100Mb Half-Duplex Mode
12
Bit Preambles Sent in 10Mb and 100Mb Operation
13
CRS Detection Takes too Long in MII Half-Duplex Mode
13
DMA Early Receive Function Does Not Work
13
ILOS Bit Copied Incorrectly from EEPROM to Speed Bits
13
Gigabit Half-Duplex Mode Operates Incorrectly
13
Zero-Byte PCI Bus Writes
14
TCP Segmentation Feature Operates Incorrectly
14
Incorrect Checksum Calculation and Indication
14
Transmitter Affected by Discarding Packets
14
Flash Memory Address Conflicts
15
Packet Buffer Memory Address Conflicts
15
Transmit Packet Corruption of Small Packets
15
Receive Packet Buffer Corruption When Nearly Full
15
Receive Packet Loss in 100Mb Half-Duplex Operation
16
TNCRS Statistic Register Has Live Count in Full-Duplex Mode
16
Receive IP Checksum Offload Disabled
16
EEPROM Initializes Software Defined Pins Incorrectly
16
82543 GC Gigabit Ethernet Controller Specification Update
17
Continuous Xoffs Transmitted When Receive Buffer Is Full
17
Default Speed Selection May Depend on EEPROM Presence
17
Link Status Change Interrupt Only Occurs if Link Is up
17
Early Transmit Feature Does Not Operate Correctly
17
TDO Output Not Floated When JTAG TAP Controller Inactive
18
Initialization Ignores Incorrect EEPROM Signature
18
Internal Loopback Difficulties
18
Collision Pin Not Ignored in TBI Mode
18
Receive Descriptor Writeback Problems for Packets Spanning Multiple Buffers
19
Illegal Oversize Packets Overflow Receive FIFO
19
Transmit Descriptor Writeback Problems with Non-Zero WTHRESH
19
Bus Initialization with some Chipsets
20
Use of Receive Delay Timer Ring Register (RDTR) Causes Occasional Lockups
20
Transmit TCP Checksum Incorrectly Modified if Calculated as 0X0000
20
Specification Clarifications
21
70C Ambient Temperature Range
21
Receiver Enabling and Disabling
21
Documentation Changes
21
TX/RX Descriptor Register Addresses
21
Auto Speed Detect Function Requires CTRL.SLU Bit to be Set
22
Values Programmed to some Registers While in Reset Do Not Persist
22
JTAG Port Operation
22
Register Summary Uses Improper Page Reference Format
23
Change O_EN_CDET Output to NO_CONNECT
23
Change Recommended Transmit IPG Programming Value for 10/100/1000BASE-T
23
Remove Transmit Report Status Sent Function
23
Remove Transmit DMA Pre-Fetching and Preemption Functions
23
Remove Gigabit Half-Duplex Transmit Burst Timer Control Function (TBT)
24
Remove Adaptive IFS Throttle Function (AIT)
24
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