Cp15 Registers; Register 0: Id & Cache Type Registers - Intel IXP45X Developer's Manual

Intel
Table 10. LDC/STC Format when Accessing CP14 (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
19:16
15:12
11:8
7:0
3.5.1

CP15 Registers

Table 11
processors.
Table 11.

CP15 Registers

Register
(CRn)
0
0
1
1
2
3
4
5
6
7
8
9
10
11 - 12
13
14
15
3.5.1.1 Register 0: ID & Cache Type Registers
Register 0 houses two read-only register that are used for part identification: an ID
register and a cache type register.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
98
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
1 1 0 P U N W L
Description
Rn - specifies the base register
CRd - specifies the coprocessor register
cp_num - coprocessor number
8-bit word offset
lists the CP15 registers implemented in the IXP45X/IXP46X network
Opcode_2
0
1
0
1
0
0
-
0
0
0
0
0
0
-
0
0
0
Rn CRd
-
-
Intel XScale
0b1111 = Undefined Exception
0b1110 = CP14
Note:
-
Access
Read / Write-Ignored
Read / Write-Ignored
Read / Write
Read / Write
Read / Write
Read / Write
Unpredictable
Read / Write
Read / Write
Read-unpredictable / Write
Read-unpredictable / Write
Read / Write
Read-unpredictable / Write
Unpredictable
Read / Write
Read / Write
Read / Write
®
Processor
8 7 6 5 4 3
cp_num 8_bit_word_offset
Notes
®
Processor defines the following:
Mappings are implementation defined
for all coprocessors below CP13.
Access to unimplemented
coprocessors (as defined by the
cpConfig bus) cause exceptions.
Description
ID
Cache Type
Control
Auxiliary Control
Translation Table Base
Domain Access Control
(Reserved)
Fault Status
Fault Address
Cache Operations
TLB Operations
Cache Lock Down
TLB Lock Down
(Reserved)
Process ID (PID)
Breakpoint Registers
(CRm = 1) CP Access
August 2006
Order Number: 306262-004US
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