Intel IXP45X Developer's Manual page 14

9.14.2.2 Port Routing Control via PortOwner and Disconnect Event ............. 413
9.14.2.3 Example Port Routing State Machine .......................................... 414
9.14.2.4 Port Power ............................................................................. 415
9.14.2.5 Port Reporting Over-Current ..................................................... 415
9.14.3 Suspend/Resume.................................................................................. 416
9.14.3.1 Port Suspend/Resume.............................................................. 416
9.14.4 Schedule Traversal Rules ....................................................................... 418
9.14.4.1 Example: Preserving Micro-Frame Integrity................................. 420
9.14.5 Periodic Schedule Frame Boundaries versus Bus Frame Boundaries ............. 423
9.14.6 Periodic Schedule ................................................................................. 425
9.14.7 Managing Isochronous Transfers Using iTDs ............................................. 426
9.14.7.1 Host Controller Operational Model for iTDs .................................. 426
9.14.7.2 Software Operational Model for iTDs .......................................... 428
9.14.8 Asynchronous Schedule ......................................................................... 430
9.14.8.1 Adding Queue Heads to Asynchronous Schedule .......................... 431
9.14.8.2 Removing Queue Heads from Asynchronous Schedule .................. 432
9.14.8.3 Empty Asynchronous Schedule Detection.................................... 435
9.14.8.4 Restarting Asynchronous Schedule Before EOF ............................ 435
9.14.8.5 Asynchronous Schedule Traversal: Start Event ............................ 438
9.14.8.6 Reclamation Status Bit (USBSTS Register) .................................. 438
9.14.9 Operational Model for Nak Counter.......................................................... 439
9.14.9.1 Nak Count Reload Control......................................................... 440
9.14.10Managing Control/Bulk/Interrupt Transfers via Queue Heads ...................... 441
9.14.10.1Fetch Queue Head ................................................................... 443
9.14.10.2Advance Queue....................................................................... 443
9.14.10.3Execute Transaction ................................................................ 444
9.14.10.4Write Back qTD ....................................................................... 449
9.14.10.5Follow Queue Head Horizontal Pointer ........................................ 449
9.14.10.6Buffer Pointer List Use for Data Streaming with qTDs ................... 449
9.14.10.7Adding Interrupt Queue Heads to the Periodic Schedule................ 451
9.14.10.8Managing Transfer Complete Interrupts from Queue Heads ........... 451
9.14.11Ping Control ......................................................................................... 452
9.14.12Split Transactions ................................................................................. 453
9.14.12.1Split Transactions for Asynchronous Transfers ............................. 453
9.14.12.2Split Transaction Interrupt........................................................ 455
9.14.12.3Split Transaction Isochronous ................................................... 468
9.14.13Host Controller Pause ............................................................................ 481
9.14.14Port Test Modes.................................................................................... 481
9.14.15Interrupts ............................................................................................ 482
9.14.15.1Transfer/Transaction Based Interrupts ....................................... 483
9.14.15.2Host Controller Event Interrupts ................................................ 485
9.15 EHCI Deviation ................................................................................................ 486
9.15.1 Embedded Transaction Translator Function............................................... 486
9.15.1.1 Capability Registers ................................................................. 487
9.15.1.2 Operational Registers............................................................... 487
9.15.1.3 Discovery ............................................................................... 487
9.15.1.4 Data Structures ...................................................................... 488
9.15.1.5 Operational Model ................................................................... 488
9.15.2 Device Operation .................................................................................. 490
9.15.2.1 USBMODE Register .................................................................. 490
9.15.2.2 EHCI Reserved Fields ............................................................... 490
9.15.2.3 SOF Interrupt ......................................................................... 491
9.15.3 Embedded Design Interface ................................................................... 491
9.15.3.1 Frame Adjust Register.............................................................. 491
9.15.4 Miscellaneous Variations from EHCI ......................................................... 491
9.15.4.1 Programmable Physical Interface Behavior.................................. 491
9.15.4.2 Discovery ............................................................................... 491
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
14
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Intel IXP45X and Intel IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US