Sent Stall (Sst); Force Stall (Fst); Receive Fifo Not Empty (Rne) - Intel IXP45X Developer's Manual

8.5.14.2 Receive Packet Complete (RPC)
The receive packet complete bit is set by the UDC when an OUT packet is received.
When this bit is set, the IR12 bit in the appropriate UDC status/interrupt register is set,
if receive interrupts are enabled.
This bit can be used to validate the other status/error bits in the endpoint 12 control/
status register. The UDCCS12[RPC] bit is cleared by writing a 1 to it. The UDC issues
NAK handshakes to all OUT tokens while this bit is set and both buffers have unread
data.
8.5.14.3 Bit 2 Reserved
Bit 2 is reserved for future use.
8.5.14.4 Bit 3 Reserved
Bit 3 is reserved for future use.
8.5.14.5

Sent Stall (SST)

The sent stall bit is set by the UDC in response to FST successfully forcing a user-
induced STALL on the USB bus. This bit is not set if the UDC detects a protocol violation
from the host PC when a STALL handshake is returned automatically. In either event,
the Intel XScale processor does not intervene and the UDC clears the STALL status
when the host sends a CLEAR_FEATURE command.
Any valid data in the FIFO remains valid and the software must unload it. The endpoint
operation continues normally and does not send another STALL condition, even if the
UDCCS12[SST] bit is set.
To allow the software to continue to send the STALL condition on the USB bus, the
UDCCS12[FST] bit must be set again. The Intel XScale processor writes a 1 to the sent
stall bit to clear it.
8.5.14.6

Force Stall (FST)

The Intel XScale processor can set the force stall bit to force the UDC to issue a STALL
handshake to all OUT tokens. STALL handshakes continue to be sent until the Intel
XScale processor clears this bit by sending a Clear Feature command.
The UDCCS12[SST] bit is set when the STALL state is actually entered, but this may be
delayed if the UDC is active when the UDCCS12[FST] bit is set. The UDCCS12[FST] bit
is automatically cleared when the UDCCS12[SST] bit is set.
To ensure that no data is transmitted after the Clear Feature command is sent and the
host resumes IN requests, software must clear the transmit FIFO by setting the
UDCCS12[FTF] bit.
8.5.14.7

Receive FIFO Not Empty (RNE)

The receive FIFO not empty bit indicates that unread data remains in the receive FIFO.
This bit must be polled when the UDCCS12[RPC] bit is set to determine if there is any
data in the FIFO that the Intel XScale processor did not read.
The receive FIFO must continue to be read until this bit clears or data will be lost.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
320
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—USB 1.1 Device
Controller
August 2006
Order Number: 306262-004US