Register Legend; Pmu Register Table; Detailed Register Descriptions - Intel IXP45X Developer's Manual

Performance Monitoring Unit (PMU)—Intel
Processors
16.5.2 Reset Conditions
The ESR defaults to Mode Halt upon reset: performance monitoring is disabled and all
counters are disabled in this mode. The Programmable Event Counters (PECRx) values
are cleared upon reset.
16.6

Detailed Register Descriptions

Table 256.

Register Legend

Attribute
RV
PR
RS
RW
RW1C
The performance monitoring facility on the IXP45X/IXP46X network processors consists
of 13 memory-mapped registers for controlling operation and monitoring various
events. Each register appears to be 32-bits wide to the APB bus. Each of these registers
is accessed as a memory-mapped 32-bit register with a unique memory address.
Access is accomplished through regular memory-format instructions from the Bus
Interface Unit.
Table 257
Table 257.

PMU Register Table

Register Name
ESR0
ESR1
(Reserved)
(Reserved)
PSR
PMR
PMSR
(Reserved)
PEC0
PEC1
PEC2
PEC3
PEC4
PEC5
PEC6
PEC7
August 2006
Order Number: 306262-004US
®
IXP45X and Intel
Legend
Reserved RC
Preserved RO
Read/Set WO
Read/Write NA
Normal Read
RW1S
Write '1' to clear
presents the registers and their offset address.
Reset Hex Value
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
0x00000000
®
IXP46X Product Line of Network
Attribute Legend
Read Clear
Read Only
Write Only
Not Accessible
Normal Read
Write '1' to set
Hex Offset Address
0x00000000
0x00000004
0x00000008
0x0000000C
0x00000010
0x00000014
0x00000018
0x0000001C
0x00000020
0x00000024
0x00000028
0x0000002C
0x00000030
0x00000034
0x00000038
0x0000003C
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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