Uart Fifo Trigger Level; Register Legend - Intel IXP45X Developer's Manual

Universal Asynchronous Receiver-Transmitter (UART)—Intel
Product Line of Network Processors
Table 248.

UART FIFO Trigger Level

Interrupt Trigger Level [7:6]
The UART must be configured prior to transmitting and receiving data to and from the
UART. The Transmit Holding Register (THR) is used to transmit characters over the
UART interface. The Receive Buffer Register is used to receive characters from the
UART interface.
Transmitting UART data can be implemented using FIFO Mode or Non-FIFO mode. In
FIFO mode, writing a character to the Transmit Holding Register will put data on the top
of the transmit FIFO. In Non-FIFO mode, writing a character to the Transmit Holding
Register will put data in the Transmit Holding Register. The next character transmitted
will be the character contained in the Transmit Holding Register.
If characters less than 8 bits are sent, the characters will need to be right-justified. For
example, if a 5-bit data character is to be transmitted with a binary value of
The data written to the Transmit Holding Register will need to be written as
hexadecimal 0x0B.
Receiving UART data can be implemented using FIFO Mode or Non-FIFO mode. In FIFO
mode, reading a character from the Receive Buffer Register will read a character from
the bottom of the receive FIFO. In Non-FIFO mode, reading a character from the
Receive Buffer Register will read the data contained in the Receive Buffer Register. The
next character received will be the character contained in the Receive Buffer Register.
If characters less than 8 bits are received, the characters will need to be right-justified.
For example, if a 5-bit data character is received having a binary value of 00101. The
data read from the Receive Buffer Register will be a hexadecimal 0x05. (Notice that the
three most-significant bits of the byte are filled with zeros.)
The UART transmit data pin is logic 1 and the transmit FIFO and receive FIFO pointers
are initialized to the empty value after reset.
14.5 Register Descriptions
There are 13 registers which monitor and control the UART. The registers are all 32 bits
in size, but only the lower 8 bits have valid data. The UART registers share nine address
locations in the I/O address space.
Note that the state of the Divisor Latch Bit (DLAB) — the most-significant bit of the
Serial Line Control Register — affects the selection of certain of the UART registers. The
DLAB bit must be set high by the system software to access the Baud Rate Generator
Divisor Latches.
Table 249.

Register Legend

Attribute
RV
PR
August 2006
Order Number: 306262-004US
00 1 byte or more in the FIFO causes an interrupt
01 8 bytes or more in the FIFO causes an interrupt
10 16 bytes or more in the FIFO causes an interrupt
11 32 bytes or more in the FIFO causes an interrupt
Legend Attribute
Reserved RC
Preserved RO
Intel
® ®
IXP45X and Intel IXP46X
Description
Legend
Read Clear
Read Only
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
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