Pci Doorbell Register; Ahb-To-Pci Dma Ahb Address Register 0 - Intel IXP45X Developer's Manual

Network processors
Table of Contents

Advertisement

®
PCI Controller—Intel
IXP45X and Intel
10.5.3.16

PCI Doorbell Register

Register Name:
Block
0xC00000
Base Address:
The Intel XScale processor writes this register to generate an
interrupt to an external PCI device on PCI_INTA_N. Any bit set to a
1 will generate the PCI interrupt if the PCI doorbell interrupt is
enabled (pci_inten.PDBEN = 1). This register is write-1-to-set from
AHB and write-1-to-clear from PCI. The Intel XScale processor
Register Description:
writes a 1 to a bit or pattern of bits to generate the interrupt. The
external PCI device reads the register and writes 1(s) to clear the
bit(s) and deassert the interrupt. If the DBT (Doorbell Test) bit is
set in the pci_csr register, all bits become read/write from the AHB
bus.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
AHB generated doorbell interrupt to PCI. Normally read/write-1-to-set
31:0
PDB
from AHB and read/write-1-to-clear from PCI. Read/write from the AHB
side if Doorbell Test mode is enabled by setting pci_csr.DBT to a 1.
10.5.3.17

AHB-to-PCI DMA AHB Address Register 0

Register Name:
Block
0xC00000
Base Address:
Source address on the AHB bus for AHB-to-PCI DMA transfers.
Paired with pci_atpdma1_ahbaddr to allow buffering of DMA
Register Description:
transfer requests.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits
Name
31:2
address
AHB word address
1:0
Lower AHB address bits hard-wired to zero.
August 2006
Order Number: 306262-004US
®
IXP46X Product Line of Network Processors
pci_pcidoorbell
Offset Address
PDB
pci_pcidoorbell
Description
pci_atpdma0_ahbaddr
Offset Address
address
pci_atpdma0_ahbaddr
Description
®
Intel
IXP45X and Intel
0x3c
Reset Value
Access:
8
7
6
5
4
Reset
Value
0x0000
0000
0x40
Reset Value
Access:
8
7
6
5
4
Reset
Value
0x0000
0000
00
®
IXP46X Product Line of Network Processors
Develepor's Manual
0x00000000
(See below.)
3
2
1
0
PCI
AHB
Access
Access
RW1S
(RW if
RW1C
pci_csr.
DBT=1)
0x00000000
(See below.)
3
2
1
0
0
0
PCI
AHB
Access
Access
RO
RW
RO
RO
569

Advertisement

Table of Contents
loading

This manual is also suitable for:

Ixp46x

Table of Contents