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(Reserved)
Table 135.
USBSTS – USB Status (Sheet 1 of 2)
Field
(Reserved)
AS
PS
RCL
HCH
R
(Reserved)
SRI
(Reserved)
AAI
SEI
FRI
®
®
Intel
IXP45X and Intel
IXP46X Product Line of Network Processors
Developer's Manual
376
®
®
IXP45X and Intel
IXP46X Product Line of Network Processors—USB 2.0 Host Controller
These bits are reserved and should be zero.
Asynchronous Schedule Status — Read Only. 0=Default. This bit reports the current real
status of the Asynchronous Schedule. When set to zero the asynchronous schedule status is
disabled and if set to one the status is enabled. The Host Controller is not required to
immediately disable or enable the Asynchronous Schedule when software transitions the
Asynchronous Schedule Enable bit in the USBCMD register. When this bit and the Asynchronous
Schedule Enable bit are the same value, the Asynchronous Schedule is either enabled (1) or
disabled (0).
Only used by the host controller.
Periodic Schedule Status — Read Only. 0=Default. This bit reports the current real status of
the Periodic Schedule. When set to zero the periodic schedule is disabled, and if set to one the
status is enabled. The Host Controller is not required to immediately disable or enable the
Periodic Schedule when software transitions the Periodic Schedule Enable bit in the USBCMD
register. When this bit and the Periodic Schedule Enable bit are the same value, the Periodic
Schedule is either enabled (1) or disabled (0).
Only used by the host controller.
Reclamation — Read Only. 0=Default. This is a read-only status bit used to detect an empty
asynchronous schedule.
Only used by the host controller.
HCHaIted — Read Only. 1=Default. This bit is a zero whenever the Run/Stop bit is a one. The
Host Controller sets this bit to one after it has stopped executing because of the Run/Stop bit
being set to 0, either by software or by the Host Controller hardware (e.g. internal error).
Only used by the host controller.
(Reserved). These bits are reserved and should be zero.
(Reserved) - These bits are reserved and should be zero
SOF Received – R/WC. 0=Default.
In host mode, this bit will be set every 125us and can be used by host controller driver as a
time base.
Software writes a 1 to this bit to clear it.
This is a non-EHCI status bit.
(Reserved) - These bits are reserved and should be zero
Interrupt on Async Advance — R/WC. 0=Default. System software can force the host
controller to issue an interrupt the next time the host controller advances the asynchronous
schedule by writing a one to the Interrupt on Async Advance Doorbell bit in the USBCMD
register. This status bit indicates the assertion of that interrupt source.
Only used by the host controller.
System Error— R/WC. This bit is not used in this implementation and will always be set to
"0".
Frame List Rollover — R/WC. The Host Controller sets this bit to a one when the Frame List
Index rolls over from its maximum value to zero. The exact value at which the rollover occurs
depends on the frame list size. For example. If the frame list size (as programmed in the Frame
List Size field of the USBCMD register) is 1024, the Frame Index Register rolls over every time
FRINDEX [1 3] toggles. Similarly, if the size is 512, the Host Controller sets this bit to a one
every time FHINDEX [12] toggles.
Only used by the host controller.
AS PS
Description
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7
6
5
4
3
2
August 2006
Order Number: 306262-004US
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0
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