Intel IXP45X Developer's Manual page 747

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HSS Coprocessor—Intel IXP45X and Intel
Byte interleaving involves disregarding four in every 16 timeslots (as shown in
Figure 182). The first four timeslots are unassigned except for the framing pulse. The
following 4 bytes are byte 0 of each T1 frame. The next 4 bytes are byte 1 of each T1
frame. The next 4 bytes are byte 2 of each T1 frame. The following 4 bytes are again
unassigned. Unassigned timeslots are dictated by the look up tables.
Frame interleaving T1 frames onto this backplane bus would be to process the first T1
frame in its entirety starting with the first timeslot and finishing on the 24
the frame bit/pulse is located on the last bit of the 32
The second T1 frame is then processed and so on until all 4 frames are processed, this
fills the entire 128 timeslots available. This mode is also programmable by the NPE
Core.
August 2006
Reference Number: 306262-004US
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IXP46X Product Line of Network Processors
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Intel IXP45X and Intel
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IXP46X Product Line of Network Processors
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