E1 Rx Frame, Externally Generated Frame Pulse; Line-Card Mode - Intel IXP45X Developer's Manual

Figure 175. E1 RX Frame, Externally Generated Frame Pulse
hss_rx_clock
hss_rx_frame
data1
hss_rx_data
By using the IxHssAcc API, the following settings should be considered when
configuring HSS interface for E1 operation:
• Frame size 256 bits (for E1).
• Frame sync simultaneous with first bit in first timeslot – TX frame offset and RX
frame offset should be set due to HSS logic, different values due to external device
can be accommodated.
• Select use of input/output TX/RX frame syncs.
• Select use of input/output clock, and clock speed.
• Select negative/positive clock for generating/sampling frame in transmit/receive.
• Select negative/positive clock for generating/sampling data in transmit/receive.
• Frame sync active level (high/low).
• MSb/LSb-first ordering for transmit and receive.
• Data polarity, maintain or invert.
• Select to not use FBit at frame start.
• Select value for idle timeslots on transmit and unused bit in 56k timeslots.
• Select buffer size.
• Configure lookup tables.
13.5.3 GCI
The HSS hardware has support to allow connection to a General Circuit Interface (GCI).
This interface is also sometimes referred to as an IOM (ISDN Oriented Modular)
interface. The HSS hardware supports two basic modes of operation for GCI protocol:

• Line-Card Mode

• Termination Mode
13.5.3.1 Line-Card Mode
The General Circuit Interface (also know as IOM) is a serial data stream consisting of
8000 frames, 4 slots per frame and each slot is a byte wide. It is used to exchange
Bearer channel data (PCM-coded voice) and control information.
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
740
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Intel IXP45X and Intel
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IXP46X Product Line of Network Processors—HSS Coprocessor
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B4246-02
August 2006
Reference Number: 004US