Ddri Sdram Pipelined Writes; Ddri Sdram Refresh Cycle - Intel IXP45X Developer's Manual

Figure 116. DDRI SDRAM Pipelined Writes
Notes:
- DI b, etc. = Data In for column b, etc.
- DI b', etc. = the next Data in following DI b, etc. according to the programmed burst order
- Burst Length = 4 is shown.
- Write command may be to any bank and may be in the same or different devices.
11.2.2.12

DDRI SDRAM Refresh Cycle

Since the DDRI SDRAM is a dynamic memory, the MCU issues a refresh cycle
periodically. The interval of these refresh cycles is programmable in the RFR register.
The DDRI SDRAM device generates the refresh address internally. The MCU initiates
two sequential refresh cycles (one per bank) after the MCUs refresh timer expires and
any current transaction is complete. To preserve the correct refresh period, the refresh
timer continues counting after it expires to prevent a gradual skewing of the refresh
interval. The waveform in
expires while the memory bus is not busy.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
612
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Intel IXP45X and Intel
T0 T1
CK_N
CK
Command Write
Bank
Address
Col b
ADDRESS Max
DQS
DI vs Do
DM
= Don't Care
Figure 117
IXP46X Product Line of Network Processors—Memory Controller
T2 T3 T4 T5
Write Write
Bank Bank
Col x Col n
Do Do Do
b b' x
illustrates the case where the refresh timer
T6 T7 T8 T9
Write Write
Bank Bank
Col a Col g
Do Do Do Do
x' n n' a
Order Number: 306262-004US
Do
a'
B0408-02
August 2006