Input Meta-Stability Protection, Edge Detect Logic, Pulse Discrimination; Clock Generation - Intel IXP45X Developer's Manual

the same bit in the General-Purpose Data Output Register — and the corresponding bit
in the General-Purpose Enable Register is still set to a logic 0 — logic 0 will be
replicated to the corresponding GPIO.
For example, the General-Purpose Enable Register is set to hexadecimal 0xFFFFFAFF
and the General-Purpose Data Output Register is set to hexadecimal 0x00000401.
GPIO8 and GPIO 10 will be configured as outputs, GPIO8 will drive logic 0, and GPIO10
will drive logic 1.
Notice that bit 0 of the General-Purpose Data Output Register is set to logic 1. However,
GPIO0 is configured as an input so the logic 1 in the General-Purpose Data Output
Register is not replicated to GPIO0.
Reading of the current status of the GPIO can be obtained by reading the General-
Purpose Input Status Register. The General-Purpose Input Status Register is a 16-bit
register with a one-for-one correspondence between the 16 bits of the General-Purpose
Input Status Register and the 16-bit GPIO.
When reading the General-Purpose Input Status Register, the current logic value of the
GPIO will be reflected in the corresponding bits of the General-Purpose Input Status
Register. The values will be replicated regardless of the configuration of the GPIO as
defined by the General-Purpose Enable Register.
If a GPIO is configured as an output, the value driven to the output will be read when
reading the corresponding bits of the General-Purpose Input Status Register.
example, the General-Purpose Enable Register is set to hexadecimal 0xFFFFFAFF and
the General-Purpose Data Output Register is set to hexadecimal 0x00000401 and the
GPIO pins have the following signals being supplied as inputs or driven as outputs,
hexadecimal 0xAE37 with GPIO[15:12] = A and GPIO[3:0] = 7. GPIO8 and GPIO10 are
configured as outputs as defined by the General-Purpose Enable Register. All other
GPIO pins are configured as inputs. When the General-Purpose Input Status Register is
read the value of hexadecimal 0x0000AE37 will be returned.
15.4.1 Input Meta-Stability Protection, Edge Detect Logic, Pulse
Discrimination
The GPIO input pin will be sampled through a synchronizer cell to provide meta-
stability protection.
For the interrupt detection logic the pulse width of the synchronized GPIO input is
monitored to ensure that it is greater than four pclk cycles. This discriminates against
small pulses and ensures that glitches are not detected. A counter based approach is
used to monitor the pulse width. A valid condition, which depends on the interrupt
detect type programmed in the GPIT registers, is used to enable the counter. Once the
count has reached four pclk cycles the appropriate bit is set in the GPISR register. Each
programmed input pin of GPIO0 through GPIO 12 can detect active high, active low,
rising, falling or transitional (rising/falling) interrupts.
15.4.2

Clock Generation

The GPIO block provides two programmable clock outputs. The clocks are generated by
counters based on the APB clock, pclk. There are two register settings which control the
operation of the clock generator, one to define the terminal count (TC) of the counter,
the other to define the duty cycle (DC). The counters are 4-bit up counters (i.e.,
counting from zero to the TC), free running at the pclk rate. Therefore, the TC defines
the clock period. The Duty Cycle (DC) represents the number of counts for which
output clock is low. There is one special condition defined; if TC = F and DC = F, then
the output of the clock generator block will be pclk/2. If the duty cycle (DC) is
programmed to be greater than or equal to the Terminal Count (TC), the generator
outputs a '1'.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
778
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors—GPIO Controller
For
August 2006
Reference Number: 306262-004US