Overflow Flag Status Register - Intel IXP45X Developer's Manual

Intel
Table 60. Interrupt Enable Register (Sheet 2 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: [4:0] = 0b00000, others unpredictable
Bits
2
1
0
3.7.2.5

Overflow Flag Status Register

FLAG identifies which counter has overflowed and also indicates an interrupt has been
requested if the overflowing counter's corresponding interrupt enable bit (contained
within INTEN) is asserted. An overflow is cleared by writing a '1' to the overflow bit.
Table 61. Overflow Flag Status Register (Sheet 1 of 2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
reset value: [4:0] = 0b00000, others unpredictable
Bits
31:5
4
3
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
160
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Intel XScale
Access
Read / Write
Read / Write
Read / Write
Access
Read-unpredictable / Write-as-0
Read / Write
Read / Write
8
Description
PMN1 Interrupt Enable (P1) -
0 = disable interrupt
1 = enable interrupt
PMN0 Interrupt Enable (P0) -
0 = disable interrupt
1 = enable interrupt
CCNT Interrupt Enable (C) -
0 = disable interrupt
1 = enable interrupt
8
Description
Reserved
PMN3 Overflow Flag (P3) -
Read Values:
0 = no overflow
1 = overflow has occurred
Write Values:
0 = no change
1 = clear this bit
PMN2 Overflow Flag (P2) -
Read Values:
0 = no overflow
1 = overflow has occurred
Write Values:
0 = no change
1 = clear this bit
Order Number: 306262-004US
®
Processor
7 6 5 4 3 2 1 0
P P P P
C
3 2 1 0
7 6 5 4 3 2 1 0
P P P P
C
3 2 1 0
August 2006