Intel IXP45X Developer's Manual page 8

6.2.33 Address Mask 3 .................................................................................... 259
6.2.34 Address Mask 4 .................................................................................... 259
6.2.35 Address Mask 5 .................................................................................... 259
6.2.36 Address Mask 6 .................................................................................... 260
6.2.37 Address Registers ................................................................................. 260
6.2.38 Address 1 ............................................................................................ 261
6.2.39 Address 2 ............................................................................................ 261
6.2.40 Address 3 ............................................................................................ 261
6.2.41 Address 4 ............................................................................................ 262
6.2.42 Address 5 ............................................................................................ 262
6.2.43 Address 6 ............................................................................................ 262
6.2.44 Threshold for Internal Clock ................................................................... 263
6.2.45 Unicast Address Registers ...................................................................... 263
6.2.46 Unicast Address 1 ................................................................................. 264
6.2.47 Unicast Address 2 ................................................................................. 264
6.2.48 Unicast Address 3 ................................................................................. 264
6.2.49 Unicast Address 4 ................................................................................. 264
6.2.50 Unicast Address 5 ................................................................................. 265
6.2.51 Unicast Address 6 ................................................................................. 265
6.2.52 Core Control ........................................................................................ 265
7.0 UTOPIA Level 2 ......................................................................................................268
7.1 Introduction .................................................................................................... 268
7.2 UTOPIA Transmit Module .................................................................................. 269
7.3 UTOPIA Receive Module .................................................................................... 272
7.4 UTOPIA Level 2 Coprocessor / NPE Coprocessor: Bus Interface .............................. 275
7.5 MPHY Polling Routines ...................................................................................... 275
7.6 UTOPIA Level 2 Clocks...................................................................................... 276
8.0 USB 1.1 Device Controller.......................................................................................278
8.1 USB Overview ................................................................................................. 278
8.2 Device Configuration ........................................................................................ 279
8.3 USB Operation ................................................................................................ 280
8.3.1 Signalling Levels................................................................................... 280
8.3.2 Bit Encoding......................................................................................... 281
8.3.3 Field Formats ....................................................................................... 282
8.3.4 Packet Formats .................................................................................... 283
8.3.4.1
8.3.4.2
8.3.4.3
8.3.4.4
8.3.5 Transaction Formats.............................................................................. 285
8.3.5.1
8.3.5.2
8.3.5.3
8.3.5.4
8.3.6 UDC Device Requests ............................................................................ 287
8.3.7 UDC Configuration ................................................................................ 288
8.4 UDC Hardware Connections............................................................................... 289
8.4.1 Self-Powered Device ............................................................................. 289
8.4.2 Bus-Powered Devices ............................................................................ 289
8.5 Register Descriptions........................................................................................ 289
8.5.1 UDC Control Register ............................................................................ 291
8.5.1.1
8.5.1.2
8.5.1.3
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
8
® ®
Intel IXP45X and Intel
Token Packet Type .................................................................. 284
Start-of-Frame Packet Type ...................................................... 284
Data Packet Type .................................................................... 284
Handshake Packet Type ........................................................... 285
Bulk Transaction Type.............................................................. 285
Isochronous Transaction Type ................................................... 286
Control Transaction Type.......................................................... 286
Interrupt Transaction Type ....................................................... 287
UDC Enable ............................................................................ 291
UDC Active ............................................................................. 292
UDC Resume (RSM)................................................................. 292
IXP46X Product Line of Network Processors-Contents
August 2006
Order Number: 306262-004US