Page Hit/Miss Logic For 128/256/512/1, 024-Bit Mode - Intel IXP45X Developer's Manual

If the current transaction hits the open page, then the page is already active and the
read or write command may be issued without a row-activate command. When the next
transaction is the same command type as the current transaction, and also a page hit,
the MCU does not need to issue the command again, but simply drive column address
for an open page.
If the refresh timer expires and the MCU issues an auto-refresh command, all pages are
closed.
Figure 114
Figure 117.
miss in Figure
Figure 104. Page Hit/Miss Logic for 128/256/512/1, 024-Bit Mode
Bank 0
Bank 0
Bank 0
Bank 0
Bank 1
Bank 1
Bank 1
Bank 1
Pag e Reg ist erSelect
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
596
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Intel IXP45X and Intel
illustrates the performance benefit of a read hit versus a read miss in
Figure 115 illustrates the performance benefit of a write hit versus a write
120.
Leaf 0
Leaf 1
Leaf 2
Leaf 3
Leaf 0
Leaf 1
Leaf 2
Leaf 3
IXP46X Product Line of Network Processors—Memory Controller
Pag e Reg ist er
Valid Open Page Address 0
Valid Open Page Address 1
Valid Open Page Address 2
Valid Open Page Address 3
Valid Open Page Address 4
Valid Open Page Address 5
Valid Open Page Address 6
Valid Open Page Address 7
PageComparator
PageHit
B4209-001
August 2006
Order Number: 306262-004US