Adding Queue Heads To Asynchronous Schedule - Intel IXP45X Developer's Manual

USB 2.0 Host Controller—Intel
determine when the asynchronous schedule has made the desired transition. Software
must not modify the Asynchronous Schedule Enable bit unless the value of the
Asynchronous Schedule Enable bit equals that of the Asynchronous Schedule Status
bit.
The asynchronous schedule is used to manage all Control and Bulk transfers. Control
and Bulk transfers are managed using queue head data structures. The asynchronous
schedule is based at the ASYNCLISTADDR register. The default value of the
ASYNCLISTADDR register after reset is undefined and the schedule is disabled when
the Asynchronous Schedule Enable bit is a zero.
Software may only write this register with defined results when the schedule is
disabled, for example, Asynchronous Schedule Enable bit in the USBCMD and the
Asynchronous Schedule Status bit in the USBSTS register are zero. System software
enables execution from the asynchronous schedule by writing a valid memory address
(of a queue head) into this register. Then software enables the asynchronous schedule
by setting the Asynchronous Schedule Enable bit is set to one. The asynchronous
schedule is actually enabled when the Asynchronous Schedule Status bit is a one.
When the host controller begins servicing the asynchronous schedule, it begins by
using the value of the ASYNCLISTADDR register. It reads the first referenced data
structure and begins executing transactions and traversing the linked list as
appropriate. When the host controller "completes" processing the asynchronous
schedule, it retains the value of the last accessed queue head's horizontal pointer in the
ASYNCLISTADDR register. Next time the asynchronous schedule is accessed, this is the
first data structure that will be serviced. This provides round-robin fairness for
processing the asynchronous schedule.
A host controller "completes" processing the asynchronous schedule when one of the
following events occur:
• The end of a micro-frame occurs.
• The host controller detects an empty list condition (i.e. see
"Empty Asynchronous Schedule Detection" on page
• The schedule has been disabled via the Asynchronous Schedule Enable bit in the
USBCMD register.
The queue heads in the asynchronous list are linked into a simple circular list as shown
in Figure 55, "General Format of Asynchronous Schedule List" on page
head data structures are the only valid data structures that may be linked into the
asynchronous schedule. An isochronous transfer descriptor (iTD or siTD) in the
asynchronous schedule yields undefined results.
The maximum packet size field in a queue head is sized to accommodate the use of this
data structure for all non-isochronous transfer types. The USB Specification, Revision
2.0 specifies the maximum packet sizes for all transfer types and transfer speeds.
System software should always parameterize the queue head data structures according
to the core specification requirements.
9.14.8.1

Adding Queue Heads to Asynchronous Schedule

This is a software requirement section. There are two independent events for adding
queue heads to the asynchronous schedule. The first is the initial activation of the
asynchronous list. The second is inserting a new queue head into an activated
asynchronous list.
Activation of the list is simple. System software writes the physical memory address of
a queue head into the ASYNCLISTADDR register, then enables the list by setting the
Asynchronous Schedule Enable bit in the USBCMD register to a one.
August 2006
Order Number: 306262--, Revision: 004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Intel
435)
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IXP45X and Intel IXP46X Product Line of Network Processors
Section 9.14.8.3,
419. Queue
Developer's Manual
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