Instruction Cache; Operation When Instruction Cache Is Enabled; Example Of Locked Entries In Tlb - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
Only entries 0 through 30 can be locked in either TLB; entry 31can never be locked. If
the lock pointer is at entry 31, a lock operation will update the TLB entry with the
translation and ignore the lock. In this case, the round-robin pointer will stay at
entry 31.
Figure 5.

Example of Locked Entries in TLB

Eight entries locked, 24 entries available for
round robin replacement
entry 0
entry 1
entry 7
entry 8
entry 22
entry 23
entry 30
entry 31
3.2

Instruction Cache

The Intel XScale processor instruction cache enhances performance by reducing the
number of instruction fetches from external memory. The cache provides fast execution
of cached code. Code can also be locked down when guaranteed or fast access time is
required.
Figure 6
access the cache.
The instruction cache is available as a 32 K, 32-way set, associative cache. Each set is
1,024 bytes in size. Each set contains 32 ways. Each way of a set contains eight 32-bit
words and one valid bit, which is referred to as a line. The replacement policy is a
round-robin algorithm and the cache also supports the ability to lock code in at a line
granularity.
The instruction cache is virtually addressed and virtually tagged.
Note: The virtual address presented to the instruction cache may be remapped by the PID
register. For a description of the PID register, see
page 106.
3.2.1

Operation When Instruction Cache is Enabled

When the cache is enabled, it compares every instruction request address against the
addresses of instructions that it is currently holding. If the cache contains the
requested instruction, the access "hits" the cache, and the cache returns the requested
instruction. If the cache does not contain the requested instruction, the access "misses"
the cache. The cache requests an eight-word, also known as a line, fetch from external
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
shows the cache organization and how the instruction address is used to
B4326-01
"Register 13: Process ID" on
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Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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