Intel IXP45X Developer's Manual page 898

Intel
Register
Bits Name
Arbitration
Arbitration Loss Detected Interrupt Enable:
Loss
0 = Disable interrupt.
12 Detected
1 = Enables the I
Interrupt
Enable
Slave STOP Detected Interrupt Enable:
Slave STOP
Detected
0 = Disable interrupt.
11
Interrupt
1 = Enables the I
Enable
Bus Error Interrupt Enable:
0 = Disable interrupt.
1 = Enables the I
Bus Error
• As a master transmitter, no Ack was detected after a byte was
10 Interrupt
Enable
• As a slave receiver, the I
Note:
IDBR Receive Full Interrupt Enable:
IDBR Receive
0 = Disable interrupt.
09 Full Interrupt
1 = Enables the I
Enable
IDBR
IDBR Transmit Empty Interrupt Enable:
Transmit
0 = Disable interrupt.
08 Empty
1 = Enables the I
Interrupt
Enable
General Call Disable:
0 = Enables the I
General Call
07 1 = Disables I
Disable
This bit must be set when sending a master mode general call
message from the I
2
I C Unit Enable:
0 = Disables the unit and does not master any transactions or
2
I C Unit
06
Enable
1 = Enables the I
Software must guarantee the I
SCL Enable:
05 SCL Enable
0 = Disables the I
1 = Enables the I
Master Abort: used by the I
a STOP without transmitting another data byte.
0 = The I
1 = The I
When in Master transmit mode, after transmitting a data byte, the
ICR's Transfer Byte bit is cleared and IDBR Transmit Empty bit is set.
04 Master Abort
When no more data bytes need to be sent, setting master abort bit
sends the STOP. The Transfer Byte bit (03) must remain clear.
In master-receive mode, when a Nack is sent without a STOP (STOP
ICR bit was not set) and the IXP45X/IXP46X network processors do
not send a repeated START, setting this bit sends the STOP. Once
again, the Transfer Byte bit (03) must remain clear.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
898
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—I2C Bus Interface Unit
I
Description
2
C unit to interrupt the IXP45X/IXP46X network
processors upon losing arbitration while in master mode.
2
C unit to interrupt the IXP45X/IXP46X network
processors upon detecting a STOP condition while in slave mode.
2
C unit to interrupt the IXP45X/IXP46X network
processors for the following I
sent.
2
C unit generated a Nack pulse.
Software is responsible for guaranteeing that misplaced
START and STOP conditions do not occur. See
"Glitch Suppression Logic" on page
2
C unit to interrupt the IXP45X/IXP46X network
processors when the IDBR has received a data byte from the I
bus.
2
C unit to interrupt the IXP45X/IXP46X network
processors after transmitting a byte onto the I
2
C unit to respond to general call messages.
2
C unit response to general call messages as a slave.
2
C unit.
respond to any slave transactions.
2
C unit (defaults to slave-receive mode).
2
C bus is idle before setting this bit.
2
C unit from driving the SCL line.
2
C clock output for master mode operation.
2
C unit when in master mode to generate
2
C unit transmits STOP using the STOP ICR bit only.
2
C unit sends STOP without data transmission.
2
C Control Register (Sheet 2 of 3)
2
C bus errors:
Section 21.8,
896.
2
C bus.
Reset
Access
Value
0 RW
0 RW
0 RW
0 RW
2
C
0 RW
0 RW
0 RW
0 RW
0 RW
August 2006
Order Number: 306262-004US