Ts_Channel_Control Register (Per Channel) - Intel IXP45X Developer's Manual

Intel
19.5.2.16

TS_Channel_Control Register (Per Channel)

Register Name:
Block
RegBlockAddress
Base Address:
Time Synchronization Channel Control Register
Register Description:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
Register
Bits Name
31:2 (Reserved) Reserved for future use.
Timestamp All messages.
• When this bit is set, the locking of the time snapshot registers is inhibited.
1 ta
• When this bit is cleared, the timestamp taken after the SFD is frozen or
Master Mode.
• When this bit is set, it indicates that this channel is a time master on the
0 mm
• When cleared, this bit indicates that this channel is in slave mode.
The default after reset is slave mode.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
848
® ®
IXP45X and Intel IXP46X Product Line of Network Processors—Time Synchronization
Offset Address
Reserved
*Address offsets per channel...
Channel 0 = 0x040
Channel 1 = 0x060
Channel 2 = 0x080
Description
Each message is timestamped at the reception of a start of frame
delimiter (SFD), regardless of whether the message is a Sync or Delay
Request message. The timestamp is captured by the Snapshot register
which is never locked and therefore must be read before the next SFD is
received.
locked when a valid Sync or Delay Request message is detected, until the
software resets it.
network.
TS_Ch_Control
0x040*
Reset Value
8
TS_Ch_Control
Hardware Assist (TSYNC)
x00
Access: (See below.)
7 6 5 4 3 2 1
Reset
Access
Value
x x
0 RW
0 RW
August 2006
Order Number: 306262-004US
0