T1 Tx Frame, Hss Generating Frame Pulse; T1 Tx Frame Using External Frame Pulse - Intel IXP45X Developer's Manual

®
HSS Coprocessor—Intel IXP45X and Intel
Figure 170. T1 TX Frame, HSS Generating Frame Pulse
hss_tx_clock
hss_tx_frame _out_en
hss_tx_frame_out
hss_tx_data_out _en
hss_tx_data_out
Figure 170
posedge clock for generating data. If the frame pulse was generated with a negedge
clock, the frame pulse in
The same location applies to the data when being generated on the negedge of the
clock.
In Figure 170
FIFO. The HSS knows which time slot in the FIFO is holding the F Bit, as it knows from
the time slot counter and frame offset when the F Bit should be transmitted.
Figure 171. T1 TX Frame Using External Frame Pulse
hss_tx_clock
hss_tx_frame
hss_tx_data_out_en
hss_tx_data_out
Figure 172
and a positive edge clock for sampling data.
August 2006
Reference Number: 306262-004US
®
IXP46X Product Line of Network Processors
FBit data1 data2
illustrates a typical T1 frame with active high frame sync (level) and a
Figure 170
and Figure 171, the FBit to be transmitted is stored in the HSS Transmit
FBit data1 data2
illustrate a typical T1 received frame with an active high frame sync (level)
data 191
would be located one half clock space to the right.
data3 data4
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
data 192 FBit data1
data5 data7 data8
B4239-02
Developer's Manual
B4238-02
737