Internal Accumulator Access Format - Intel IXP45X Developer's Manual

®
Intel XScale Processor—Intel
The instruction is only executed if the condition specified in the instruction matches the
condition code status.
3.8.3.1.2

Internal Accumulator Access Format

The Intel XScale processor defines a new instruction format for accessing internal
accumulators in CP0.
shows that the op code falls into the coprocessor register transfer space.
The RdHi and RdLo fields allow up to 64 bits of data transfer between Intel
StrongARM
accumulators to transfer data to/from. The Intel XScale processor implements a single
40-bit accumulator referred to as acc0; future implementations can specify multiple
internal accumulators of varying sizes, up to 64 bits.
Access to the internal accumulator is allowed in all processor modes (user and
privileged) as long bit 0 of the Coprocessor Access Register is set. (See
Coprocessor Access Register" on page 107
The IXP45X/IXP46X network processors implement two instructions MAR and MRA
that move two Intel
StrongARM
Table 69. Internal Accumulator Access Format
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
cond
Bits
31:28
20
19:16
15:12
7:4
3
2:0
Note: MAR has the same encoding as MCRR (to coprocessor 0) and MRA has the same
encoding as MRRC (to coprocessor 0). These instructions move 64-bits of data to/from
®
Intel StrongARM
defined in Intel
Disassemblers not aware of MAR and MRA will produce the following syntax:
MCRR{<cond>} p0, 0x0, RdLo, RdHi, c0
MRRC{<cond>} p0, 0x0, RdLo, RdHi, c0
August 2006
Order Number: 306262-004US
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Table 69, "Internal Accumulator Access Format" on page 173
*
registers and an internal accumulator. The acc field specifies 1 of 8 internal
® *
StrongARM
*
registers, respectively.
1 1 0 0 0 1 0 L
Description
® *
cond - Intel StrongARM condition codes
L - move to/from internal accumulator
0= move to internal accumulator (MAR)
1= move from internal accumulator (MRA)
RdHi - specifies the high order eight (39:32)
bits of the internal accumulator.
RdLo - specifies the low order 32 bits of the
internal accumulator
Should be zero
Should be zero
acc - specifies 1 of 8 internal accumulators
*
registers from/to coprocessor registers. MCRR and MRRC are
® *
StrongARM 's DSP instruction set.
Intel
for more details).
registers to acc0 and move acc0 to two Intel
RdHi RdLo 0
-
-
On a read of the acc, this 8-bit high order field
will be sign extended.
On a write to the acc, the lower 8 bits of this
register will be written to acc[39:32]
-
-
Intel XScale processor only implements acc0;
access to any other acc is unpredictable
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
®
"Register 15:
®
8 7 6 5 4 3 2
0 0 0 0 0 0 0 0
Notes
Developer's Manual
1 0
acc
173