Interrupt Enable Register; Register Legend; Receive Buffer Register; Uart Registers Overview - Intel IXP45X Developer's Manual

Intel
Table 249.

Register Legend

Attribute
RS
RW
RW1C
The following sample register-summary table indicates, in parentheses, which
paragraph tags are cross-referenced in the individual register tables.
Table 250.

UART Registers Overview

Address
0xC800_X000†
0x C800_X004
0x C800_X008
0x C800_X00C
0x C800_X010
0x C800_X014
0x C800_X018
0x C800_X01C
0x C800_X020
† The X in the value C800_X000 is used to denote that this could be a value of either 0 or 1 depending
upon if it is UART 0(High Speed UART) or UART 1(Console UART), respectively. This is the same for
all other addresses to the UARTs.
14.5.1

Receive Buffer Register

Register Name:
0xC800 X000
Hex Offset Address:
Register
Receive Buffer Register
Description:
Access: Read Only.
31
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IXP45X and Intel IXP46X Product Line of Network Processors—Universal Asynchronous
Legend
Read/Set
Read/Write
Normal Read
Write '1' to clear
DLAB Access
0 RO
0 WO
1 RW
0 RW
1 RW
0/1 RO
0/1 WO
0/1 RW
0/1 RW
0/1 RO
0/1 RO
0/1 RW
0 RW
(Reserved)
Attribute Legend
WO Write Only
NA Not Accessible
Normal Read
RW1S
Write '1' to set
Name
RBR Receive Buffer Register
THR Transmit Holding Register
DLL Divisor Latch Low Register
IER

Interrupt Enable Register

DLH Divisor Latch High Register
IIR Interrupt Identification Register
FCR FIFO Control Register
LCR Line Control Register
MCR Modem Control Register
LSR Line Status Register
MSR Modem Status Register
SPR Scratch-Pad Register
ISR Slow Infrared Select Register
RBR
0x00000000
Reset Hex Value:
Receiver-Transmitter (UART)
Description
8 7
RBR
August 2006
Order Number: 306262-004US
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