Intel IXP45X Developer's Manual page 624

Referring to
indicated by the appropriate row of the G-Matrix in
ECC bit. For example, the MCU derives syndrome bit 0 by XORing data bits 0, 4, 8, 12,
16, 20, 25, 29..31, 40..43, 48..56, 58, 59, 62, and ECC bit 0 (physically read on
DDRI_CB[7:0]). The MCU performs eight such XOR operations (one per syndrome bit).
If decoding the syndrome indicates multi-bit error (see
results in a target-error for Internal Bus transactions, or a multi-bit error in the BIU for
Core transactions. If an internal bus master detects a target-abort, the master asserts
an interrupt to the core. Write cycles are posted to the memory transaction queues,
and already completed to the initiating master. For write cycles with a multi-bit error
and with ECC Error reporting enabled, the MCU reports the interrupt in the MCISR and
interrupts the core.
If the syndrome indicates a single-bit error and single-bit error correction is enabled,
the H-Matrix is used to determine the bit in error (see
syndrome was 1100 0001, the error is with bit 0 of DDRI_DQ[31:0]. The MCU inverts
bit 0 before driving the data on DATA[63:0].
If error reporting is enabled in the ECCR and the MCU detects a single-bit or multi-bit
error, the MCU stores the address in ECARx and the syndrome in ELOGx. Then, the
MCU signals an interrupt to the core. Software decides how to proceed through an
interrupt handler. By registering the address in ECARx, software can identify the faulty
DIMM.
For details about the MCU error conditions and how the MMR registers are affected,
refer to
Note: In 32-bit wide memory, the DDRI SDRAM Control Block will still generate 8-bit wide
ECC by zero-extending the data to 64-bits. A partial write is a write of less than
4 Bytes.
11.2.3.4 Scrubbing
Fixing the data error in memory is called scrubbing. The IXP45X/IXP46X network
processors rely on Intel XScale processor software to perform the scrubbing. When the
MCU detects an error during a read, the MCU logs the address where the error occurred
and interrupts the Intel XScale processor. The Intel XScale processor decides how to fix
the error through an interrupt handler. Software could decide to perform the scrubbing
on:
• the data location that failed
• the entire row of the data that failed
• the entire memory
For single-bit errors reported on a write transaction scrubbing is not required, as the
MCU will have scrubbed the data during the RMW operation. For single-bit errors, the
error is fixed by reading the location that failed and writing back the data after the ECC
hardware fixed it. The scrubbing routine should read either DWORD of the 64-bit
memory space (QWORD aligned location) using an ld instruction and write the data
back with an st instruction. Software should isolate activity on the memory location to
guarantee atomicity.
Note: If the scrubbing routine reads the failed location in order to fix the single-bit error, a
second error will be reported. Therefore, software should disable single-bit ECC
reporting during the scrubbing routine. Also, the scrubbing routine should be aware
that partial writes will automatically scrub the QWORD aligned location if it contains a
single-bit ECC error.
Multi-bit errors cannot be fixed by the H-Matrix.
® ®
Intel IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
624
® ®
Intel IXP45X and Intel
Figure 121, the syndrome bits are created by XORing the data bits as
"Interrupts/Error Conditions" on page
IXP46X Product Line of Network Processors—Memory Controller
Figure 119
627.
with the corresponding
Table 213), the transaction
Figure 122). For example, if the
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August 2006