Data Alignment - Intel IXP45X Developer's Manual

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Intel XScale Processor—Intel
• The stack space of a frequently occurring interrupt, the stack is used only during
the duration of the interrupt, which is usually very small.
• Video buffers, these are usual large and can occupy the whole cache.
Over use of the Mini-Data cache will thrash the cache. This is easy to do because the
Mini-Data cache only has two ways per set. For example, a loop which uses a simple
statement such as:
for (i=0; I< IMAX; i++)
{
A[i] = B[i] + C[i];
}
Where A, B, and C reside in a mini-data cache memory region and each is array is
aligned on a 1-K boundary will quickly thrash the cache.
3.10.4.2.6

Data Alignment

Cache lines begin on 32-byte address boundaries. To maximize cache line use and
minimize cache pollution, data structures should be aligned on 32-byte boundaries and
sized to multiple cache line sizes. Aligning data structures on cache address boundaries
simplifies later addition of prefetch instructions to optimize performance.
Not aligning data on cache lines has the disadvantage of moving the prefetch address
correspondingly to the misalignment. Consider the following example:
struct {
long ia;
long ib;
long ic;
long id;
} tdata[IMAX];
for (i=0, i<IMAX; i++)
{
PREFETCH(tdata[i+1]);
tdata[i].ia = tdata[i].ib + tdata[i].ic _tdata[i].id];
....
tdata[i].id = 0;
}
In this case if tdata[] is not aligned to a cache line, then the prefetch using the address
of tdata[i+1].ia may not include element id. If the array was aligned on a cache line +
12 bytes, then the prefetch would halve to be placed on &tdata[i+1].id.
If the structure is not sized to a multiple of the cache line size, then the prefetch
address must be advanced appropriately and will require extra prefetch instructions.
Consider the following example:
August 2006
Order Number: 306262-004US
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IXP45X and Intel IXP46X Product Line of Network Processors
Intel
® ®
IXP45X and Intel IXP46X Product Line of Network Processors
Developer's Manual
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